STE2004 datasheet(6/66 Pages) STMICROELECTRONICS

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STE2004

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CIRCUIT DESCRIPTION

3.1 Supplies Voltages and Grounds

VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is

not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage

could be different form VDD2.

3.2 Internal Supply Voltage Generator

The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display

supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using

the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have

the lowest current consumption in every condition. This make possible to have an input voltage that chang-

es over time and a constant VLCD voltage. The output voltage (VLCD) is tightly controlled through the VL-

CDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with

temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast

degradation over the LCD operating range.

An external supply could be connected to VLCD to supply the LCD without using the internal generator. In

such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset con-

dition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.

3.3 Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock for the Dis-

play System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be

used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004

is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more

drivers.

3.4 Master/Slave Mode

STE2004 support the Master Slave working Mode for Both Control Logic and Charge Pump. This function

allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004 and the internal

Charge Pump of both device.

If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master

Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The

Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references.

If M/S is connected to GND, the driver is configured to work in Slave Mode. When STE2004 is in Slave

Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register

are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so

the slave configuration can follow the master configuration. The only recognized configuration is Vop=0

that forces the Charge Pump to be in off state whatever is the value of Vsense_aux.

To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Mas-

ter Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT

Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven

together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on

the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or

to VDD1_aux (Fig. 5).

During Power Up Procesure, Master device must be forced to exit from power down before the slave de-

vice. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master De-

vice.

DD2

2VLCD

⋅

()

-------------------------

200mV

≥

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