STE2004 datasheet(38/66 Pages) STMICROELECTRONICS

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STE2004

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No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).

The start of Checker-board procedure will be between one and two fclock cycles from the last active edge

(E falling edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL

rising edge for the I2C interface).

5.5 Scrolling Function

The STE2004 can scroll the graphics display in units of raster-rows. The scrolling function is achieved

changing the correspondence between the rows of the logical memory map and the output row drivers.

The scroll function doesn't affect the data ram content. It is only related to the visualization process. The

information output on the drivers is related to the row reading sequence (the 1st row read is output on R0,

the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially in-

creased or decreased. After every scrolling command the offset between the memory address and the

memory scanning pointer is increased or decreased by one. The offset range changes in accordance with

MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling com-

mands in mux 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the

memory address and the memory scanning pointer is again zero (Cyclic Scrolling).

A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory ad-

dress and the memory scanning pointer

If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose

row and it is scrolled as other lines.

If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top

down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled

from bottom-up.

Table 8.

5.6 Dual Partial Display

If the PE Bit is set to a logic one the dual partial display mode is enabled.

Eight partial display modes are available. The offset of the two partial display zones is row by row pro-

grammable. The Icon row is accessed last in each partial display frame.

Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].).

This allows switching from normal mode to partial display mode only with one instruction. The HV gener-

ator is automatically re configured using the parameters related to the enabled mode. The parameters of

the two sets of registers with the same function are located in the same position of the instruction set. The

registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are

accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0],

CP[2:0] values the instruction flow proposed in Fig. 54 must be followed. To setup Partial Display Sectors

Start Address and Partial Display Mode no particular instruction flow has to be followed.

MUX RATE

ICON MODE

DESCRIPTION

ICON Row Driver with MY=0

MUX 33

ICON ROW NOT SCROOLED

R48

MUX 33

33 LINE GRAPHIC MATRIX

R48

MUX 49

ICON ROW NOT SCROOLED

R56

MUX 49

49 LINE GRAPHIC MATRIX

R56

MUX 65

ICON ROW NOT SCROOLED

R64

MUX 65

65 LINE GRAPHIC MATRIX

R64

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