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STE2004 数据表(PDF) 47 Page - STMicroelectronics |
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STE2004 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 66 page  47/66 STE2004 Figure 60. Host Processor Interconnection with 4-line SPI Interface Figure 61. Host Processor Interconnection with 3-line SPI Interface DIGITAL VDD STE2004 µP D/C CS RES D0 D1 D2 D3 D4 D5 D6 D7 VSSAUX VSSAUX E - WR R/W - RD SDIN-SDAIN SDOUT SDAOUT SCLK-SCL SEL2 SEL3 SEL1 VSS TEST_MODE VDD1 VDD2 LR0111 VDD1 ANALOG VDD VSSAUX ICON VDD1 / VSSAUX VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE VDD1_AUX OSC_IN FR_IN SA1 VSSAUX M/S SA0 TEST VREF VDD1 VDD1 / VSSAUX EXT_SET DIGITAL VDD STE2004 µP D/C CS RES D0 D1 D2 D3 D4 D5 D6 D7 VSSAUX VSSAUX E - WR R/W - RD SDIN-SDAIN SDOUT SDAOUT SCLK-SCL SEL2 SEL3 SEL1 VSS TEST_MODE VDD1 VDD2 LR0112 VSSAUX ANALOG VDD VDD1 VSSAUX ICON VDD1 / VSSAUX VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE VDD1_AUX OSC_IN FR_IN SA1 VSSAUX M/S SA0 TEST VREF VDD1 VDD1 / VSSAUX EXT_SET |
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