STM32U545NET6QTR datasheet(55/283 Pages) STMICROELECTRONICS

55 / 283 page

DS14216 Rev 1

55/283

STM32U545xx

Functional overview

•

256 x 16-bit local memory

•

Up to three areas can be defined in memory for data buffers (two input, one output),

defined by programmable base address pointers and associated size registers

•

Input and output buffers can be circular

•

Filter functions: FIR, IIR (direct form 1)

•

Vector functions: dot product, convolution, correlation

•

AHB slave interface

•

DMA read and write data channels

3.23

Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial

NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with

the following functional modes:

•

Indirect mode: all the operations are performed using the OCTOSPI registers.

•

Status-polling mode: the external memory status register is periodically read and

an interrupt can be generated in case of flag setting.

•

Memory-mapped mode: the external memory is memory mapped and is seen by the

system as if it were an internal memory supporting read and write operation.

The OCTOSPI supports the following protocols with associated frame formats:

•

the standard frame format with the command, address, alternate byte, dummy cycles

and data phase

•

the HyperBus™ frame format

The OCTOSPI offers the following features:

•

Three functional modes: Indirect, Status-polling, and Memory-mapped

•

Read and write support in Memory-mapped mode

•

Supports for single, dual, quad and octal communication

•

Dual-quad mode, where eight bits can be sent/received simultaneously by accessing

two quad memories in parallel.

•

SDR (single-data rate) and DTR (double-transfer rate) support

•

Data strobe support

•

Fully programmable opcode

•

Fully programmable frame format

•

HyperBus support

•

Integrated FIFO for reception and transmission

•

8-, 16-, and 32-bit data accesses allowed

•

DMA channel for Indirect mode operations

•

Interrupt generation on FIFO threshold, timeout, operation complete, and access error

3.23.1

OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.

Up to two nonsecure area can be configured thought the TZSC MPCWM1 controller with

a granularity of 64 Kbytes.

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