STM32U545NET6QTR datasheet(72/283 Pages) STMICROELECTRONICS

72 / 283 page

Functional overview

STM32U545xx

72/283

DS14216 Rev 1

•

Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,

corresponding to one block size

•

AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB

error is generated)

•

8 × 32-bit words (H0 to H7) for output message digest

•

Automatic data flow control with support of direct memory access (DMA) using one

channel. Single or fixed burst of 4 supported.

•

Interruptible message digest computation, on a per-32-bit word basis

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Re-loadable digest registers

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Hashing computation suspend/resume mechanism, including using DMA

3.37

On-the-fly decryption engine (OTFDEC)

The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request

address information, for example execute-in-place of a code stored encrypted. Four

independent and non-overlapping encrypted regions can be defined in OTFDEC.

OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency.

As consequence, each time the content of one encrypted region is changed the entire

region must be re-encrypted with a different cryptographic context (key or initialization

vector). This constraint makes OTFDEC suitable to decrypt read-only data or code, stored in

external NOR Flash.

Note:

When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the Flash

memory using the Memory-mapped mode of the Flash memory controller.

When security is enabled in the product, OTFDEC can be programmed only by

a secure host.

The OTFDEC main features are the following:

•

On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations

(single or multiple)

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Use of AES in counter (CTR) mode, with two 128-bit keystream buffers

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Support for any read size

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Physical address of the reads is used for the encryption/decryption

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Up to 4 independent encrypted regions

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Granularity of the region definition: 4096 bytes

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Region configuration write locking mechanism

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Each region has its own 128-bit key, two bytes firmware version, and eight bytes

application-defined nonce. At least one of those must be changed each time

an encryption is performed by the application.

•

Encryption keys confidentiality and integrity protection

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Write-only registers, with software locking mechanism

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Availability of 8-bit CRC as public key information

•

Support for OCTOSPI prefetching mechanism

•

Possibility to select an enhanced encryption mode to add a proprietary layer of

protection on top of AES stream cipher (execute only)

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