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STM32U545NET6QTR 数据表(PDF) 28 Page - STMicroelectronics

部件名 STM32U545NET6QTR
功能描述  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, 512 KB flash memory, 274 KB SRAM, crypto
PDF  283 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32U545NET6QTR 数据表(HTML) 28 Page - STMicroelectronics

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Functional overview
STM32U545xx
28/283
DS14216 Rev 1
3.6.1
TrustZone peripheral classification
When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows:
securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure
3.6.2
Default TrustZone security state
The default system security state is detailed below:
CPU:
Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
Memory map:
SAU is fully secure after reset. Consequently, all memory map is fully secure.
Up to eight SAU configurable regions are available for security attribution.
Flash memory:
Flash memory security area is defined by watermark user options.
Flash memory block based area is nonsecure after reset.
SRAMs:
All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
External memories:
OCTOSPI banks are secure after reset. MPCWMx (memory protection watermark
based controller) is secure.
Peripherals
Securable peripherals are nonsecure after reset.
TrustZone-aware peripherals are nonsecure after reset. Their secure configuration
registers are secure.
All GPIOs are secure after reset.
Interrupts:
NVIC: All interrupts are secure after reset. NVIC is banked for secure and
nonsecure state.
TZIC: All illegal access interrupts are disabled after reset.
3.7
Boot modes
At startup, a BOOT0 pin, NBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that
includes:
Boot from any address in user flash memory.
Boot from system memory bootloader.
Boot from any address in embedded SRAM.
Boot from RSS (root security services).



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