STM32U545NET6QTR datasheet(21/283 Pages) STMICROELECTRONICS

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DS14216 Rev 1

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STM32U545xx

Functional overview

•

Close to zero wait-states instructions/data access performance:

–

0 wait-state on cache hit

–

Hit-under-miss capability, allowing to serve new processor requests while a line

refill (due to a previous cache miss) is still ongoing

–

Critical-word-first refill policy, minimizing processor stalls on cache miss

–

Hit ratio improved by two-ways set-associative architecture and pLRU-t

replacement policy (pseudo-least-recently-used, based on binary tree), algorithm

with best complexity/performance balance

–

Dual master ports allowing to decouple internal and external memory traffics, on

fast and slow buses, respectively; also minimizing impact on interrupt latency

–

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

–

Performance monitoring by means of a hit counter and a miss counter

•

Extension of cacheable region beyond the code memory space, by means of address

remapping logic that allows four cacheable external regions to be defined

•

Power consumption reduced intrinsically (more accesses to cache memory rather to

bigger main memories); even improved by configuring ICACHE as direct mapped

(rather than the default two-ways set-associative mode)

•

TrustZone security support

•

Maintenance operation for software management of cache coherency

•

Error management: detection of unexpected cacheable write access, with optional

interrupt raising

3.2.2

Data cache (DCACHE)

The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the

performance of data traffic to/from external memories.

DCACHE offers the following features:

•

Multi-bus interface:

–

Slave port receiving the memory requests from the Cortex-M33 S-AHB system

port

–

Master port performing refill requests to external memories (external flash memory

and RAMs through Octo-SPI)

–

Second slave port dedicated to DCACHE registers access

•

Close to zero wait-states external data access performance:

–

Zero wait-states on cache hit

–

Hit-under-miss capability, allowing to serve new processor requests to cached

data, while a line refill (due to a previous cache miss) is still ongoing

–

Critical-word-first refill policy for read transactions, minimizing processor stalls on

cache miss

–

Hit ratio improved by two-ways set-associative architecture and pLRU-t

replacement policy (pseudo-least-recently-used, based on binary tree), algorithm

with best complexity/performance balance

–

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

–

Performance monitoring by means of two hit counters (for read and write) and two

miss counters (for read and write)

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