STM32U545NET6QTR datasheet(38/283 Pages) STMICROELECTRONICS

38 / 283 page

Functional overview

STM32U545xx

38/283

DS14216 Rev 1

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the

user to select one of the low-power modes described below:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop 0, Stop 1, Stop 2, and Stop 3 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. The SRAMs can be totally or partially switched off to further

reduce consumption. All clocks in the VCORE domain are stopped, the PLL, the MSI,

the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is

still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals are autonomous and can operate in Stop mode by requesting their

kernel clock and their bus (APB or AHB) when needed, in order to transfer data with

DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2

modes). Refer to Low-power background autonomous mode (LPBAM) for more details.

LPBAM is not supported in Stop 3 mode.

In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage mode.

Stop 0 and Stop 1 modes offer the largest number of active peripherals and wake-up

sources, a smaller wake-up time but a higher consumption than Stop 2 mode.

In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time but

with much higher consumption.

Stop 3 is the lowest power mode with full retention, but the functional peripherals and

sources of wake-up are reduced to the same ones than in Standby mode.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI

up to 24 MHz or HSI16, depending on software configuration.

1. LPR means that the main regulator is OFF and the low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can

also be put in power-down mode.

4. The SRAM1, SRAM2, SRAM4 and BKPSRAM clocks can be gated on or off independently.

5. The SRAM can be individually powered off to save power consumption.

6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from

Stop event detections.

7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on

conversion events.

8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also

called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.

9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can

generate a wake-up interrupt on transfer events.

10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up

interrupt on transfer events.

11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up

interrupt on transfer events.

12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on all events.

13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on events.

14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wake-up interrupt on events.

15. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

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