STM32U545NET6QTR datasheet(40/283 Pages) STMICROELECTRONICS

40 / 283 page

Functional overview

STM32U545xx

40/283

DS14216 Rev 1

Those peripherals support the features detailed below:

•

Functionality in Stop mode thanks to its own independent clock (named kernel clock)

request capability: the peripheral kernel clock is automatically switched on when

requested by a peripheral, and automatically switched off when no peripheral

requests it.

•

DMA transfers supported in Stop mode thanks to system clock request capability: the

system clock (MSI or HSI16) automatically switched on when requested by

a peripheral, and automatically switched off when no peripheral requests it. When the

system clock is requested by an autonomous peripheral, the system clock is woken up

and distributed to all peripherals enabled in the RCC. This allows the DMA to access

the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO

registers).

•

Automatic start of the peripheral thanks to hardware synchronous or asynchronous

triggers (such as I/Os edge detection and low-power timer event).

•

Wake-up from Stop mode with peripheral interrupt.

The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode,

allowing the different DMA transfers to be linked without any CPU wake-up. This can be

used to chain different peripherals transfers, or to write peripherals registers in order to

change their configuration while remaining in Stop mode.

The DMA transfers from memory to memory can be started by hardware synchronous or

asynchronous triggers, and the DMA transfers between peripherals and memories can also

be gated by those triggers.

Here below some use-cases that can be done while remaining in Stop mode:

•

A/D or D/A conversion triggered by a low-power timer (or any other trigger)

–

wake-up from Stop mode on analog watchdog if the A/D conversion result is out of

programmed thresholds

–

wake-up from Stop mode on DMA buffer event

•

Audio digital filter data transfer into SRAM

–

wake-up from Stop on sound-activity detection

•

I2C slave reception or transmission, SPI reception, UART/LPUART reception

–

wake-up at the end of peripheral transfer or on DMA buffer event

•

I2C master transfer, SPI transmission, UART/LPUART transmission, triggered by

a low-power timer (or any other trigger):

–

example: sensor periodic read

–

wake-up at the end of peripheral transfer or on DMA buffer event

•

Bridges between peripherals

–

example: ADC converted data transferred by communication peripherals

•

Data transfer from/to GPIO/LPGPIO to/from SRAM for:

–

controlling external components

–

implementing data transmission and reception protocols

STM32U545NET6QTR 数据表(PDF) 40 Page - STMicroelectronics

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