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STM32U545NET6QTR 数据表(PDF) 137 Page - STMicroelectronics |
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STM32U545NET6QTR 数据表(HTML) 137 Page - STMicroelectronics |
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137 / 283 page ![]() DS14216 Rev 1 137/283 STM32U545xx Electrical characteristics 258 5.3.2 Operating conditions at power-up/power-down The parameters given in the table below are derived from tests performed under the ambient temperature condition summarized in Table 33. 5.3.3 Embedded reset and power control block characteristics The parameters given in the table below are derived from tests performed under the ambient temperature conditions summarized in Table 33. 6. The I/Os powered by VSW are: - PC13, PC14, PC15 when VDD is present. - PC13, PC14, PC15, and all FT_t I/Os in VBAT mode. 7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max. Table 34. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Max Unit tVDD VDD rise-time rate - 0 ∞ µs/V VDD fall-time rate ULPMEN = 0 (default value) 20 ∞ Standby mode, BOR level 0 selected with ULPMEN = 1 250 ∞ ms/V Table 35. Embedded reset and power control block characteristics(1) Symbol Parameter Conditions Min Typ Max Unit tRSTTEMPO(2) Reset temporization after BOR0 is detected VDD rising - - 900 μs |
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