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STM32U535NET6QTR 数据表(PDF) 47 Page - STMicroelectronics |
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STM32U535NET6QTR 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 278 page  DS14217 Rev 1 47/278 STM32U535xx Functional overview 84 Figure 5. Clock tree MSv70518V1 SYSCLK MCO LSCO 48 MHz clock to USB To ADC1, ADC4 and DAC1 To IWDG To RTC HCLK To AHB bus, core, memory and DMA FCLK Cortex free running clock To Cortex system timer To APB1 peripherals To APB2 peripherals PCLK1 PCLK2 LSE HSI16 To USARTx (x = 3, 4, 5) To I2Cx (X = 1,2,4) To LPTIM2 AUDIOCLK To TIMx (x = 2 to 7) OSC32_OUT OSC32_IN MSIS HSI16 HSE HSE HSI16 /32 AHB PRESC /1,2,..512 / 8 APB1 PRESC /1,2,4,8,16 x1 or x2 HSI16 LSI LSE HSI16 APB2 PRESC /1,2,4,8,16 To TIMx (x = 1,8,15,16,17) x1 or x2 To USART1 LSE HSI16 SYSCLK / M HSI RC 16 MHz HSE OSC 4-50 MHz Clock detector OSC_OUT OSC_IN LSI RC 32 kHz or 250 Hz HSI16 LSI LSE HSE SYSCLK HSI48 MSIS To OCTOSPI1 To SDMMC1 / M HSI48 RC 48 MHz CRS clock ICLK LSE OSC 32.768 kHz Clock detector MSIS 100 kHz – 48 MHz MSIK 100 kHz – 48 MHz MSI RC MSIK HSI16 To SPI2 LSE LSI x4 x3 MSIK HSE pll1_q_ck pll2_p_ck To FDCAN1 MSIS MSIK pll1_r_ck HSI48 pll1_p_ck MSIK LSI MSIS HSI16 HSE PLL3 / M pll3_p_ck pll3_q_ck pll3_r_ck MSIS HSI16 HSE SYSCLK MSIK pll1_q_ck MSIK HSI16 SYSCLK To SPI1 pll1_p_ck pll2_p_ck pll3_p_ck HSI16 To SAI1 x2 pll1_p_ck pll3_q_ck MSIK To ADF1 and MDF1 / 2 HSI16 To RNG x2 HSI48 MSIK pll1_q_ck pll2_q_ck To APB3 peripherals PCLK3 APB3 PRESC /1,2,4,8,16 pll2_r_ck HSE HSI16 MSIK x2 LSI LSE DAC1 sample and hold clock SYSCLK SYSCLK SYSCLK LSE To SPI3 To I2C3 To LPUART1 To PWR HSI16 MSIK HSI16 MSIK HSI16 MSIK MSIK HSI16 LSI LSE To LPTIM1, LPTIM3, LPTIM4 Clock source control / Q / P / R VCO / N PLL2 / Q / P / R VCO / N pll2_p_ck pll2_q_ck pll2_r_ck PLL1 / Q / P / R VCO / N pll1_p_ck pll1_q_ck pll1_r_ck pll2_q_ck |
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