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STM32U535NET6QTR 数据表(PDF) 83 Page - STMicroelectronics |
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STM32U535NET6QTR 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 278 page  DS14217 Rev 1 83/278 STM32U535xx Functional overview 84 • Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4 • CAN FD with maximum 64 data bytes supported • CAN error logging • AUTOSAR and J1939 support • Improved acceptance filtering • 2 receive FIFOs of three payloads each (up to 64 bytes per payload) • Separate signaling on reception of high priority messages • Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload) • Configurable transmit Event FIFO • Programmable loop-back test mode • Maskable module interrupts • Two clock domains: APB bus interface and CAN core kernel clock • Power-down support 3.44 USB full speed (USB) USB main features • USB specification version 2.0 full-speed compliant • Host and device functions • 2048 bytes of dedicated SRAM data buffer memory with 32-bit access • USB clock recovery • Configurable number of endpoints from 1 to 8 • Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted (NRZI) encoding/decoding, and bit-stuffing • Isochronous transfers support • Double-buffered bulk/isochronous endpoint support • USB suspend/resume operations • Frame-locked clock pulse generation • USB 2.0 Link power management support • Battery charging specification revision 1.2 support in device 3.45 Development support 3.45.1 Serial-wire/JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. |
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