STM32U535NET6QTR datasheet(76/278 Pages) STMICROELECTRONICS

76 / 278 page

Functional overview

STM32U535xx

76/278

DS14217 Rev 1

3.39

Universal synchronous/asynchronous receiver transmitter

(USART/UART)

and low-power universal asynchronous receiver transmitter

(LPUART)

The devices embed two universal synchronous receiver transmitters (USART1, USART3),

two universal asynchronous receiver transmitters (UART4, UART5) and one low-power

universal asynchronous receiver transmitter (LPUART1).

SMBus/PMBus hardware support

Independent clock

Autonomous in Stop 0, Stop 1 mode with wake-up capability

Autonomous in Stop 2 mode with wake-up capability

1. X: supported

Table 20. I2C implementation (continued)

I2C features(1)

I2C1

I2C2

I2C3

I2C4

Table 21. USART, UART and LPUART features

USART modes/features(1)

1. X = supported.

USART1/3

UART4/5

LPUART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode (master/slave)

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual-clock domain and wake-up from Stop mode

X(2)

Wake-up supported from Stop 0 and Stop 1 modes.

X(2)

X(3)

Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

Receiver timeout interrupt

Modbus communication

Auto-baud rate detection

Driver enable

USART data length

7, 8 and 9 bits

Tx/Rx FIFO

Tx/Rx FIFO size

8 bytes

Autonomous mode

STM32U535NET6QTR 数据表(PDF) 76 Page - STMicroelectronics

STM32U535NET6QTR 数据表(HTML) 76 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载