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STM32U535NET6QTR 数据表(PDF) 19 Page - STMicroelectronics |
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STM32U535NET6QTR 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 278 page  DS14217 Rev 1 19/278 STM32U535xx Description 19 Figure 1. STM32U535xx block diagram MSv70517V1 @VSW USB NJTRST, JTDI, JTCK/SWCLK, JTMS/SWDIO, JTDO TRACECLK, TRACED[3:0] JTAG/ SW MPU ETM NVIC Arm Cortex-M33 160 MHz TrustZone FPU C-BUS S-BUS D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin D0dir, D2dir SDMMC1 GPDMA1 TSC MDF1 GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port H GPIO port G 7 groups of 4 channels max as AF SDIN[1:0], CKIN[1:0], CCK0, CCK1 as AF PA[15:0] PB[15:0] PC[15:13] PD[15:0] PE[15:0] PH[1:0] PG[15:2] 97 AF 17xIN @VDDA ADC1 ITF 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1/PWM 16b 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM8/PWM 16b 2 channels, 1 compl. channel, BKIN as AF TIM15 16b 1 channel, 1 compl. channel, BKIN as AF TIM16 16b 1 channel, 1 compl. channel, BKIN as AF TIM17 16b RX, TX, CK,CTS, RTS as AF MOSI, MISO, SCK, NSS as AF SPI1 smcard irDA USART1 MCLK_A, SD_A, FS_A, SCK_A, MCLK_B, SD_B, FS_B, SCK_B as AF SAI1 SYSCFG AHB/APB2 AHB/APB1 FMAC CORDIC CRC SRAM2 (64 Kbytes) SRAM1 (192 Kbytes) Flash memory (up to 512 Kbytes) Octo-SPI1 memory interface IO[7:0], CLK, NCLK, NCS. DQS as AF RNG HASH DP DM D[15:0], CK, CMD as AF DCMI/PSSI @VDD Power management Voltage regulator LDO and SMPS 3.3 to 1.2 V VDD = 1.71 to 3.6 V VSS VDD @VDD Supply supervision BOR VDDIO, VDDUSB, VDDA, VSSA, VDD, VSS, NRST Reset PVD, PVM Int @VDD XTAL OSC 4- 50 MHz IWDG OSC_IN OSC_OUT Standby interface @VDD MSI HSI16 PLL 1, 2, 3 Reset and clock control TIM2 32b TIM3 32b TIM4 32b TIM5 32b smcard irDA UART4 UART5 SPI2 I2C1/SMBUS I2C2/SMBUS I2C4/SMBUS FDCAN1 USART3 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels RX, TX, CK, CTS, RTS as AF RX, TX, CTS, RTS as AF RX, TX, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF TX, RX as AF WWDG CRS TIM6 16b TIM7 16b LPTIM2 IN1, IN2, CH1, CH2, ETR as AF SRAM4 (16 Kbytes) LPDMA1 @VDDA D/A converter 1 ITF DAC1_OUT1 @VDDA ADC4 ITF DAC1_OUT2 15xIN LPGPIO IO[15:0] as AF ADF1 SDIN0, CKIN0, CCK0, CCK1 as AF AHB/APB3 Temperature monitoring @VSW XTAL 32k RTC RTC_OUT1, RTC_OUT2, RTC_REFIN, RTC_TS TAMP RTC_OUT[8:1], RTC_IN[8:1] @VDDA VREF buffer VREF+ @VDDA COMP1 INP, INN, OUT @VDDA OpAmp1 INP, INN, OUT LPTIM1 IN1, IN2, CH1, CH2, ETR as AF LPTIM3 IN1, IN2, CH1, CH2, ETR as AF LPTIM4 IN1, OUT, ETR as AF I2C3/SMBUS SCL, SDA, SMBA as AF SPI3 MOSI, MISO, SCK, NSS as AF LPUART1 VDD power domain VDDUSB power domain VSW power domain VDDIO2 power domain VDDA power domain RX, TX, CTS, RTS_DE as AF @VDDUSB BKPSRAM (2 Kbytes) AUDIOCLK as AF GTZC1 GTZC2 HSI48 WKUPx (x=1 to 8) Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0. PC[12:0] D/A converter 2 AHB2 160 MHz EXT IT. WKP PH[3] @VSW LSI |
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