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STM32U535NET6QTR 数据表(PDF) 37 Page - STMicroelectronics |
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STM32U535NET6QTR 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 278 page  DS14217 Rev 1 37/278 STM32U535xx Functional overview 84 Stop 2 LPR No OFF ON(5) LSE LSI BOR, PVD, PVM, RTC, TAMP, IWDG, TEMP, VREFBUF, ADC4, DAC1 (2 channels), COMP1, OPAMP1, LPUART1, SPI3, I2C3, LPTIMx (x = 1, 3, 4), ADF1, LPGPIO, LPDMA1 All other peripherals are frozen. Reset pin, all I/Os, BOR, PVD, PVM, RTC, TAMP, IWDG, TEMP, ADC4, COMP1, LPUART1, SPI3, I2C3, LPTIMx (x = 1,3,4), ADF1, LPDMA1 Stop 3 LPR No OFF ON(5) LSE LSI BOR, RTC, TAMP, IWDG, DAC1 (2 static channels), OPAMP1 All other peripherals are frozen. I/O configuration can be floating, pull-up or pull-down. Reset pin, 24 I/Os (WKUPx), BOR, RTC, TAMP, IWDG Standby LPR OFF LSE LSI BOR, RTC, TAMP, IWDG All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down. Reset pin, 24 I/Os (WKUPx), BOR, RTC, TAMP, IWDG OFF Shutdown OFF OFF LSE RTC, TAMP All other peripherals are powered off. I/O configuration can be floating, pull-up or pull-down(15). Reset pin, 24 I/Os (WKUPx), RTC, TAMP Table 9. STM32U535xx mode overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA and peripherals(2) Wake-up source |
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