数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

STM32G0C1NET7 数据表(PDF) 74 Page - STMicroelectronics

部件名 STM32G0C1NET7
功能描述  Arm® Cortex®-M0 32-bit MCU, up to 512KB Flash, 144KB RAM,6x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V
PDF  159 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32G0C1NET7 数据表(HTML) 74 Page - STMicroelectronics

Back Button STM32G0C1NET7 Datasheet HTML 70Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 71Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 72Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 73Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 74Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 75Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 76Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 77Page - STMicroelectronics STM32G0C1NET7 Datasheet HTML 78Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 74 / 159 page
background image
Electrical characteristics
STM32G0C1xC/xE
74/159
DS13564 Rev 4
Table 29. Typical current consumption in Run and Low-power run modes,
depending on code executed
Symbol
Parameter
Conditions
Typ
Unit
Typ
Unit
General
Code
Fetch
from(1)
25 °C
25 °C
IDD(Run)
Supply
current in
Run mode
Range 1;
fHCLK = fPLLRCLK =
64 MHz;
(2)
Reduced code(3)
Flash
memory
8.70
mA
136
μA/MHz
Coremark
8.15
127
Dhrystone 2.1
8.00
125
Fibonacci
7.30
114
While(1) loop
5.90
92
Reduced code(3)
SRAM
8.85
138
Coremark
9.10
142
Dhrystone 2.1
8.95
140
Fibonacci
9.85
154
While(1) loop
8.85
138
Range 2;
fHCLK = fHSI16 =
16 MHz,
PLL disabled,
(2)
Reduced code(3)
Flash
memory
2.45
153
Coremark
1.90
119
Dhrystone 2.1
1.90
119
Fibonacci
1.70
106
While(1) loop
1.35
84
Reduced code(3)
SRAM
2.10
131
Coremark
2.10
131
Dhrystone 2.1
2.05
128
Fibonacci
2.25
141
While(1) loop
2.05
128
IDD(LPRun)
Supply
current in
Low-power
run mode
fHCLK = fHSI16/8 =
2 MHz;
PLL disabled,
(2)
Reduced code(3)
Flash
memory
485
μA
243
μA/MHz
Coremark
475
238
Dhrystone 2.1
480
240
Fibonacci
500
250
While(1) loop
515
258
Reduced code(3)
SRAM
490
245
Coremark
485
243
Dhrystone 2.1
480
240
Fibonacci
510
255
While(1) loop
480
240
1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.
2. VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com