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STM32G0C1NET7 数据表(PDF) 120 Page - STMicroelectronics |
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STM32G0C1NET7 数据表(HTML) 120 Page - STMicroelectronics |
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120 / 159 page ![]() Electrical characteristics STM32G0C1xC/xE 120/159 DS13564 Rev 4 Figure 33. SPI timing diagram - master mode 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT ai14136c Table 76. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output fMCK= 256 x Fs; (Fs = audio sampling frequency) Fsmin = 8 kHz; Fsmax = 192 kHz; 2.048 49.152 MHz fCK I2S clock frequency Master data - 64xFs MHz Slave data - 64xFs DCK I2S clock frequency duty cycle Slave receiver 30 70 % |
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