Symbol Pin

Description

OPTO

7

This pin is intended to be directly connected to the collector of the optocoupler or to the output of the error

amplifier of a non-isolated topology: a pull-up current together with gain resistance is embedded in this pin.

The OPTO pin voltage is internally connected to the multiplier, together with FB pin voltage and MCP voltage

in an “OR-ed” structure.

Deep low consumption mode is invoked pulling this pin lower than the VBM threshold that features as

burst-mode level when OPTO is used.

THD

8

A ceramic capacitor is placed between this pin and SGND to set the time constant of the THD optimizer unit.

It is strongly recommended to use small package ceramic capacitors, placed as close to the above mentioned

pins as possible, to avoid any undesired noise injection.

SGND

9

Reference pin for signal’s ground potential.

ZCD

10

Multiple function pin able to detect the zero current instant, to sense the output voltage for primary side

regulation (PSR) and to compensate the peak current detection propagation delay (VFF).

The delay time between zero current instant detection and MOSFET turn-on is programmed by the resistance

between DLY/CFG pin and SGND.

An internal starter unit is active to generate the triggering signal when not externally available (for example, at

startup).

Valley skipping counter is fed by internal ZCD signal processor.

Adaptive minimum turn-off time (for example, the blanking after turn-on), larger during UVP condition, is

implemented.

CS

11

Input of the current sense comparator for the power regulation.

The current sense resistor (RCS, from primary MOSFET source to ground) must be connected to this pin

through a series resistance (RFF): this resistor is fed by an internal current, proportional to ZCD pin current

during MOSFET on time interval, that creates the offset to compensate for the PWM comparator propagation

delay.

A leading-edge blanking time avoids false triggering of the MOSFET’s turn-off due to the noise that may be

generated after gate driver turn-on.

PGND

12

Reference pin for VCC and gate driver.

GD

13

Gate driver output.

The output stage is suitable to directly drive power MOSFETs.

An internal pulldown resistor aims to keep the MOSFET off during low power operating modes.

VCC

14

Supply voltage of the IC.

Internal UVLO logic prevents the operation at voltages that are insufficient for an efficient gate driving or

internal signal processing.

Both a bulk capacitor (typically around 22 µF) and a high frequency filter capacitor (100 nF ceramic, mounted

as close to the device as possible) should be connected between this pin and PGND.

HVLED101

Pin Settings

DS14143 - Rev 2

page 5/36