Table 7. THD gate activity vs. operating modes

Operating mode

THD gate activity

Active mode (QR up to 6th valley)

GDTHD same as GD activity

Active mode (from 6th valley DCM mode)

GDTHD off (THD pin = HiZ)

Ramp-up time

GDTHD always on

Burst mode inactive phase (both PSR or OPTO)

GDTHD always on

OCP protection period

GDTHD always on

iOVP protection period

GDTHD always off (THD pin = HiZ)

Brownout protection

GDTHD always off (THD pin = HiZ)

Fault protection

GDTHD always off (THD pin = HiZ)

Auto restart time (after UVP)

GDTHD always off (THD pin = HiZ)

6.3.2

Maximum power control

The THD optimizer block lets the average value of the OPTO or FB value to be proportional to input power and

input voltage.

An internal MPC block generates a value that is derived from input voltage and that is connected in OR logic with

OPTO and FB.

Such a method allows the topology to absorb from the input source a maximum power that is independent from

input voltage and input shape.

At overloading occurrence, the IC does not take any action, but simply limits the delivered power to MPC level.

The value of current sense resistor RCS is defined by this MPC block.

RCS= KM∙KMPC

4∙NDC∙PIN_AVG

MPC block automatically detects if input voltage is AC or DC: if the input voltage does not drop below VDC-DET

for a time longer than TDC-DET, then it is assumed that a DC voltage is connected and MPC level is adjusted

accordingly, putting NDC = ½.

The AC mode is recovered (NDC = 1) at first crossing of said level.

Note that the internal peak detector is always active and triggers the maximum of any fluctuation superimposed to

HVSU voltage. If said voltage is a pure DC, the peak detector stores the input voltage itself.

Figure 9. DC detection waveforms

VDC-DET

NDC

Switching activity

TDC-DET

1/1

1/2

VHVSU

HVLED101

Control loop

DS14143 - Rev 2

page 17/36