When ramp-up mode is running, the PSR unit is functional as well.

The voltage divider connected between the transformer’s auxiliary winding and ground sets the output voltage

according to the following equation: VOUT=VREF.PSR∙NsecNaux∙ 1+RZCDRFB

Near mains zero crossing the converter manages a very low energy amount in each switching cycle. For this

reason, ZCD signal amplitude is no longer good information of the output voltage. In order to improve converter

performance (THD, PF), in such condition, the FB pin is put in high impedance and is not driven by internal OTA.

External compensation network capacitors keep the pin voltage almost constant. The zero crossing condition is

detected when the input voltage level goes below a threshold ( ≈ 70 V).

6.4.2

PSR burst-mode operation

When the output power becomes very small and frequency fold-back is no longer able to reduce the delivered

power, the flyback converter must enter burst-mode operation to maintain the output variable regulation.

When the application is regulated by an optocoupler, the secondary side error amplifier sets the repetition rate

between active and inactive phase of the burst-mode.

The PSR operation needs to generate some switching activity to refresh the content of the measurement unit.

The HVLED101 generates 4 switching cycles following a pure QR scheme (including TDLY) with a repetition time

(TREP) that is inversely proportional to the voltage that is present at the FB pin at the end of the 4 switching

cycles.

Figure 13. PSR burst-mode waveforms

TREP

VCS-MIN

1

2

3

4

VCS

GD

ICC

ICC

operating

ICC_DLC

Not in scale

VDRAIN

0.2ms

The following graph represents the relation between FB voltage and TREP.

HVLED101

Primary side regulation feature

DS14143 - Rev 2

page 21/36