When VCC drops below VCC-OFF, the IC moves to low consumption mode and activates the high-voltage startup

to recover a sufficient VCC level (VCC-ON).

6.6.2

High-voltage startup

The high-voltage startup unit is intended to charge the VCC capacitor to a voltage that is at least equal to VCC-ON.

This unit is invoked:

•

at startup

•

during low consumption to maintain the VCC level

•

during TART time to maintain the VCC level

•

in case of iOVP to discharge the input capacitor.

Two different charging currents are provided depending on the operating condition as summarized in the table

below. The charging current automatically shuts down when VCC reaches approximately 19 V.

Table 8. HVSU activation summary

Operating condition

VCC range

OFF

ICHG-H

ICHG-L

All states if VHVSU < VHV-START

Any

X

Startup (initial phase)

0 V ... VCC-LOW

X

Startup (IC startup)

VCC-LOW ... VCC-ON

X

Active mode

VCC-OFF ... VCC-ON

X

Input OVP

VCC-OFF ... VCC-AMR

X

Low consumption mode (LC)

VCC-ON ... VCC-OFF (falling)

X

VCC recover during LC mode

VCC-OFF ... VCC-ON (rising)

X

Deep low consumption mode (DLC)

Any

X

6.7

Parameter selection

Some internal parameters of the device can be programmed selecting the value of the time constant (TauCFGn)

associated with the RC network placed between DLY/CFG and GND.

Once the VCC has risen for the first time above VCC-ON, the DLY/CFG pin is pre-charged up to the VDLY-BIAS and

then released.

The DLY/CFG capacitor CCFG is then discharged by RDLY to define a time constant that is internally detected to

configure the internal parameters as per the following table.

Table 9. Programming configuration

TauCFGn (µs)

CFG

iOVP

BrOut

KHV

DC Det.

IBLEED @ iOVP

30 µs ... 45 µs

CFG1

ON

Low

High

Low

ON

100 µs ... 140 µs

CFG2

OFF

OFF

Low

Low

N.A.

300 µs ... 410 µs

CFG3

ON

High

High

High

ON

860 µs ... 1.2 ms

CFG4

OFF

Low

Low

Low

N.A.

> 2.05 ms

CFG5

ON

Low

High

Low

OFF

If the detected time is shorter than 20 µs the IC does not start, while if the time is not detected within an

approximate time of 2.05 ms, the IC autonomously proceeds into ramp-up state and sets CFG5. In this phase, the

HVSU unit is active to prevent program errors.

The following table summarizes the suggested combination of RDLY and CCFG to obtain both delay time and

configuration programming.

HVLED101

Parameter selection

DS14143 - Rev 2

page 23/36