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HVLED101 数据表(PDF) 10 Page - STMicroelectronics |
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HVLED101 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 36 page ![]() Symbol Pin/Block Parameter Test condition Min. Typ. Max. Unit TOPTO-TRIG OPTO Minimum pulse duration to exit from ramp-up phase 10.5 µs Current sense input VCS-MIN CS Current sense minimum level during burst-mode VFB < VBM 25 50 80 mV VCS-RU CS Current sense level during ramp-up During fixed frequency ramp-up phase 170 200 230 mV TLEB CS Leading edge blanking 230 300 390 ns VOCP2 CS Saturation protection threshold (2nd OCP) During on-time [TrackCS] 1.2 1.3 1.4 V VOCP1 CS Cycle-by-cycle current sense limit (1st OCP) During on-time [TrackCS] 0.837 0.9 0.963 V TOCP CS Max. stop state duration after 2nd OCP Tpulse = 1 µs, amplitude 2 V 0.72 1.04 1.41 ms TPD CS Propagation to output of current sense detection On time running, dV/dt = 0.141 V/us 80 ns KFF CS, ZCD Current gain between ZCD source current and CS pin source current On time running, IZCD = 0 to 3 mA 75 µA/mA ZCD input VZCD-TRIG ZCD ZCD triggering threshold Negative going edge [TRACKZCD] 0.16 0.2 0.26 V VZCD-ARM ZCD ZCD arming threshold Positive going edge [TRACKZCD] 0.24 0.3 0.39 V TBLANK ZCD ZCD minimum blanking time From MOSFET turn-off, with PSR S&H > VUVP 0.97 1.5 2.1 µs From MOSFET turn-off, with PSR S&H < VUVP 3.3 5.5 7.7 µs TDLY-MIN DLY/CFG ZCD trigger to GD on min. delay RDLY = 120 kΩ 355 ns TDLY-MAX DLY/CFG ZCD trigger to GD on max. delay RDLY = 270 kΩ 675 ns TWAIT-MIN ZCD ZCD waiting time after TBLANK elapse Starting from ZCD trigger, RDLY = 120 kΩ [track TDLY] 2.2 µs TWAIT-MAX ZCD Starting from ZCD trigger, RDLY = 2.7 kΩ [track TDLY] 4.8 µs VZCD-CLP-low ZCD ZCD negative clamping voltage IZCD source = 3 mA -250 mV IZCD-Bias ZCD ZCD pin biasing current VZCD = 2.7 V 1 µA VZCD-max ZCD ZCD pin max. positive voltage IZCD sink = 1mA 3 V HVLED101 Electrical characteristics DS14143 - Rev 2 page 10/36 |
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