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HVLED101TR 数据表(PDF) 12 Page - STMicroelectronics |
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HVLED101TR 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 36 page  Symbol Pin/Block Parameter Test condition Min. Typ. Max. Unit VL5 VL 5th to 6th valley threshold 1 V VDCM VL Unlocked operation limit 0.86 V KDCM VL DCM characteristic slope -130 µs / V TDCM-MAX VL Max. DCM time with linearity guaranteed VL = 0.3V 70 µs DLY/CFG pin characteristics VDLY-BIAS DLY/CFG DLY pin Bias voltage Active mode [TrackCFG] 1.5 V KDLY DLY/CFG ZCD to GD on gain 2.13 ns/kΩ VCFG-L DLY/CFG Decay hysteresis for CFG selection [TrackCFG] 0.5 V TauCFG1 DLY/CFG Time constant to set CFG1 30 45 µs TauCFG2 DLY/CFG Time constant to set CFG2 100 140 µs TauCFG3 DLY/CFG Time constant to set CFG3 300 410 µs TauCFG4 DLY/CFG Time constant to set CFG4 860 1200 µs TauCFG5 DLY/CFG Time constant to set CFG5 2050 TBD µs HVLED101 Electrical characteristics DS14143 - Rev 2 page 12/36 |
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