When the falling edge is detected, the IC can either turn on the MOSFET after the programmed delay time or start

counting the number of falling edges (valley) defined by the voltage at VL pin as per valley locking algorithm (see

relevant paragraph).

Figure 10. ZCD algorithm diagram

TBLANK ,min

N = 1

Wait ZCD

Trigger

Twait

ZCD_arm = FALSE

ZCD_trig = TRUE

AND

Nvalley > 0

T DCM

Twait

TLEB

VCS > VCS _ th

GD = OFF

GD_THD = OFF

N = 2

N = 3

N = 4

N = 5

Twait

Twait

Twait

Twait

Tdly

ZCD_arm

= TRUE

ZCD_trig = TRUE

AND

Nvalley = 0

End

OfT

wait

OR

ZCD_trig

= TRUE

AND

Fbint

> VDCM

EndOfTwait OR ZCD_trig = TRUE

AND Fbint < VDCM

En

dOf

Timer

(TDCM)

EndO

fTwait

OR ZCD_trig

= TRUE

GD =

OFF

GD_THD

= OFF

(FB =

Hi Z)

GD = ON

GD_THD = ON

6.3.5.2

Bottom valley synchronization

The pin DLY/CFG is used to adjust the delay time that the HVLED101 applies between ZCD trigger signal (falling

edge) and MOSFET turn-on.

A delay time can be programmed selecting a proper value of the resistor mounted between DLY/CFG and GND.

6.3.5.3

Valley locking and frequency fold-back

The QR flyback efficiency as well as Power Factor and THD can be improved reducing the operating frequency at

light load.

In order to maintain low turn-on losses, the frequency fold-back technique is achieved turning on the MOSFET on

the bottom of a resonance valley (valley skip).

In order to avoid random jumping between adjacent valleys (especially at high power), the valley locking scheme

is adopted and the number of jumping valleys remains constant until a significant modification of output power

or input voltage presents. As a result, input THD is minimized at intermediate load, audible noise is avoided and

output variable is smoothly regulated.

HVLED101

Control loop

DS14143 - Rev 2

page 19/36