3

Pin Settings

Figure 4. Device pinout

HVSU

N.C.

FAULT

VCC

VL

CS

PGND

GD

1

2

3

4

5

10

11

14

13

12

FB

OPTO

6

7

ZCD

8

9

DLY/CFG

SGND

THD

Table 1. Pin description

Symbol Pin

Description

HVSU

1

High-voltage startup and input voltage detection.

The pin, able to withstand 800 V, is to be connected to either the DC side of the input rectifier bridge, using a

low value resistor (1 kΩ typ), or the AC side of a rectifier bridge with two diodes.

It embeds the internal startup unit that quickly charges the capacitor connected between VCC pin and PGND

pin during startup and low consumption.

During operational mode, this pin measures the input voltage to obtain high power factor and to detect both

input overvoltage and undervoltage, according to protection configuration, selected on the DLY/CFG pin.

N.C.

2

Not connected pin for clearance.

FAULT

3

This pin is intended to stop the IC when either the voltage goes below an internal threshold or the pin is left

floating.

It is suitable to supply an NTC thermistor. The hysteresis of lower disable threshold results in a thermal

hysteresis when NTC is connected. When the functionality is unused, connect a 33 kΩ resistor between

FAULT pin and SGND.

DLY/CFG 4

The parallel of a resistor and a capacitor is connected between this pin and SGND pin: the value of the

resistance sets the delay time between ZCD detection and MOSFET turn-on, while the time constant of the

RC network selects the input detection configuration and protection. Recommended values ranges are 22 ÷

560 kΩ for R and 10 pF ÷ 100 nF for C.

VL

5

The voltage applied to this pin controls valley locking and frequency fold-back operation. It is internally biased

with a current that is proportional to the minimum between the voltages that are present at the FB pin and

at the OPTO pin (the internal FBint signal). The level of the frequency fold-back depth is set by a resistor

connected to SGND. A capacitor between the VL pin and SGND can be used to filter the fluctuations of FBint

signal.

FB

6

Output of the primary side regulation error amplifier (OTA).

The pin must be connected to the compensation network for Primary Side Regulation.

The voltage present at this pin also controls adaptive burst-mode (deep low consumption mode) and is

internally connected to the multiplier, together with OPTO pin voltage and MCP voltage in an “OR-ed”

structure.

HVLED101

Pin Settings

DS14143 - Rev 2

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