Figure 14. PSR burst-mode repetition rate

300mV

4ms

0.4ms

TREP

8ms

VBM

VFB

During the inactive phase of the burst-mode, the consumption of the HVLED101 is reduced to ICC_DLC.

During the generation of the 4 GD cycles, the current sense threshold is bottom limited to generate a minimum

demagnetization time and improve the VOUT measurement’s accuracy.

This minimum current sense level represents, in turn, a small minimum power delivered from primary to

secondary side: this minimum power delivery has to be dissipated by simple secondary side bleeder resistor

(or equivalent structure).

6.5

Gate driver

The gate driver of the HVLED101 is able to drive high and low the gate of an N-channel Silicon MOSFET, with a

typical driving strength of 1.2 A/0.6 A (sink/source).

The output of GD pin can reach VCC: care has to be taken to verify that VCC is lower than the absolute maximum

rating of the adopted switch.

6.6

IC supply management

The HVLED101 is supplied applying a DC voltage source between VCC pin and PGND.

This voltage can be easily obtained, during normal operation, by auxiliary winding of flyback transformer, but also

other voltage sources can be used.

6.6.1

VCC supply management

The HVLED101 operational scheme is designed to minimize the VCC power consumption, especially during low

consumption and deep low consumption modes.

Figure 15. UVLO and VCC regulation block diagram

VCC

VCC-ON

R

Q

S

\Q

UVLO

PGND

PWR_good

VCC-OFF

HVLED101

Gate driver

DS14143 - Rev 2

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