Figure 18. Fault pin block diagram

VFLT-ON

VFLT-Open

FLT

IFLT-BIAS

NTC

RB

RA

VFLT-OFF

The NTC can be linearized using a resistor network consisting of one resistor in series and one in parallel.

The design approach must firstly guarantee that FAULT voltage is greater than VFLT-OPEN if either the temperature

is lower than minimum operating value or the NTC is disconnected. Then the value of fault voltage is equal to

VFLT-OFF at maximum operating temperature.

The pin is also able to sense the absence of NTC, because the pin left open is internally pulled up above an

upper threshold. If NTC is not used, a fixed resistor (22 kΩ to 47 kΩ) should be connected to GND.

During FAULT pin protection, the internal THD optimizer drives the internal switched resistor always OFF (setting

δc = 0 in Section 6.3.1 ) and the THD pin is set in high impedance.

HVLED101

Protections

DS14143 - Rev 2

page 27/36