STWBC2-HP datasheet(47/96 Pages) STMICROELECTRONICS

47 / 96 page

Figure 50. Vsw switch node voltage

By consequence, checking the Vsw voltage during the probe step is sufficient to conclude that current in the coil

has reverted or not.

The current reversal information is combined with others to adjust the discharge time:

•

If current is not reverted and max. peak current in the coil is not reached, the discharge time is enlarged.

This offers more chance to drain completely the coil current during the discharge phase in order to run QR

mode.

•

If current has reverted or max. peak current in the coil is reached, the discharge time is decreased.

Reducing the discharge time helps avoiding the over-discharging of coil. In case of max. peak current,

reducing the discharge time pushes the controller in CCM mode.

•

If the output voltage overshoots the target at the end of the discharge step, the discharge time is increased.

This pushes the DC-DC duty cycle in the direction of lowering the output voltage.

2.2.7.9

Check step

The check step is simply stalling the converter while the output voltage is above the target. A new charge/

discharge cycle is engaged only if the output voltage is lower than the target.

2.2.7.10

Refresh step

Depending on the DC-DC converter topology and gate driver usage, it is possible that a toggling of a gate driver is

required to recharge the bootstrap capacitor. This is the role of these steps.

2.2.7.11

FSM control logic

The BB-DCDC main operations are controlled by an embedded finite state machine control logic.

Figure 51 shows the controller FSM state diagram:

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 47/96

STWBC2-HP 数据表(PDF) 47 Page - STMicroelectronics