STWBC2-HP datasheet(20/96 Pages) STMICROELECTRONICS

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Wait 1.5 s

Check DM voltage.

If DM voltage has felt to 0V, the dedicated charger is a high voltage one.

If DM stays > 0.4 V, the source is a simple dedicated charger.

If the source is a USB host or a simple dedicated charger, the DP and DM pins can be turned to a 20k pull-down

resistor.

If a high voltage dedicated charger is detected, the DP voltage should be maintained equal or above 0.6 V. The

USB detection circuit can be used to configure the charger to produce a desired VBUS voltage.

2.1.9

Gate drivers

The STWBC2-HP embeds 3 gate drivers designed to drive NMOS for low- and high-side using a bootstrap

technique.

Figure 25. Gate driver

All gate drivers are powered from VDD_DR and GND_DR pins. VDD_DR supports up to 10 V.

The sense and bootstrap pins are designed to support high voltage switching up to 40 V.

The gate drivers integrate their own anti-cross conduction circuit based on gate current analysis. The anti-cross

conduction circuit can be individually disabled on each gate driver. This mode allows using fixed deadtime from

PWM source directly. This mode is recommended if the gate driver is fed by the DC-DC digital controller. It can

also be needed if NMOS gate resistor is too large. In this case, the embedded anti-cross conduction circuit can be

inefficient and explicit fixed deadtime should be programmed in PWM generator.

2.1.10

PLL

The STWBC2-HP AFE embeds Phase Locked Loop IP which main purpose is to generate the accurate 17

phases required for High Resolution PWM implementation (see Section 2.2.1 for details about HR PWM).

The PLL typical operating frequency is 40 MHz.

STWBC2-HP

Analog AFE functions

DS13825 - Rev 1.0

page 20/96

STWBC2-HP 数据表(PDF) 20 Page - STMicroelectronics