STWBC2-HP datasheet(94/96 Pages) STMICROELECTRONICS

94 / 96 page

List of figures

Figure 1.

STWBC2-HP device architecture ....................................................... 3

Figure 2.

Qi single coil, fixed frequency full-bridge, USB powered ........................................ 4

Figure 3.

Qi single coil, variable frequency full-bridge, USB powered...................................... 5

Figure 4.

STWBC2-HP AFE block diagram ....................................................... 6

Figure 5.

Power management ................................................................ 7

Figure 6.

Reset strategy .................................................................... 8

Figure 7.

Boost topologies ................................................................... 8

Figure 8.

Buck topologies ................................................................... 8

Figure 9.

Buck/boost topologies ............................................................... 9

Figure 10.

BB DC-DC analog section ............................................................ 9

Figure 11.

Analog monitors .................................................................. 10

Figure 12.

VIN voltage monitor................................................................ 11

Figure 13.

Bridge voltage monitor.............................................................. 11

Figure 14.

VDD_DRIVER voltage monitor ........................................................ 12

Figure 15.

VIN current monitor ................................................................ 12

Figure 16.

Bridge current monitor .............................................................. 13

Figure 17.

Ring voltage interface .............................................................. 14

Figure 18.

USB DP/DM monitor ............................................................... 14

Figure 19.

DC-DC buck monitor ............................................................... 15

Figure 20.

Voltage demodulator ............................................................... 15

Figure 21.

Current demodulator ............................................................... 16

Figure 22.

QF driver ....................................................................... 17

Figure 23.

LED/buzzer driver ................................................................. 18

Figure 24.

USB detection ................................................................... 19

Figure 25.

Gate driver...................................................................... 20

Figure 26.

PLL........................................................................... 21

Figure 27.

Digital top level block diagram overview .................................................. 24

Figure 28.

HR-PWM block diagram overview ...................................................... 25

Figure 29.

HR-PWM subsystem overview ........................................................ 26

Figure 30.

Sequencer circuit overview........................................................... 26

Figure 31.

FSK modulation circuit overview ....................................................... 27

Figure 32.

Chronometer circuit overview ......................................................... 27

Figure 33.

Sequencer timing diagram overview .................................................... 28

Figure 34.

FSK bit streaming overview .......................................................... 30

Figure 35.

Phase modulator block diagram overview ................................................ 32

Figure 36.

Phase modulator filter machine structures overview.......................................... 33

Figure 37.

LPF (Low Pass Filter) demodulator frequency response....................................... 33

Figure 38.

HPF (High Pass Filter) demodulator frequency response ...................................... 34

Figure 39.

QF block diagram overview .......................................................... 36

Figure 40.

Gate driver and IO signal overview ..................................................... 39

Figure 41.

Multiplexer control logic ............................................................. 39

Figure 42.

Gate driver control signal configuration .................................................. 40

Figure 43.

IO mode configuration .............................................................. 40

Figure 44.

ADC_MUX block diagram overview ..................................................... 42

Figure 45.

LED_SPK block diagram overview ..................................................... 43

Figure 46.

BB-DCDC block diagram overview ..................................................... 45

Figure 47.

QR mode converged loop operation .................................................... 45

Figure 48.

DCM operation output voltage above target ............................................... 46

Figure 49.

CCM Icoil reach max. peak .......................................................... 46

Figure 50.

Vsw switch node voltage ............................................................ 47

Figure 51.

BB-DCDC FSM state diagram overview .................................................. 48

Figure 52.

BB-DCDC application topology configuration .............................................. 50

STWBC2-HP

List of figures

DS13825 - Rev 1.0

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