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STWBC2-HP 数据表(PDF) 39 Page - STMicroelectronics |
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STWBC2-HP 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 96 page ![]() Figure 40. Gate driver and IO signal overview The mux logic is composed of individual mux instance cells as shown below in Figure 41. Figure 41. Multiplexer control logic Each cell allows connecting a LS/HS couple source to a LS/HS couple output. For an asynchronous buck/boost case requiring connecting HSB and LSA for BB-DCDC to a single gate driver, the BB-DCDC integrates the capability to swap LSA and LSB on its output. Hence, the BB-DCDC source is LSA/HSB instead of LSB/HSB. The embedded gate drivers can be configured to ignore any PWM signal and to drive a constant high or low state. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 39/96 |
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