STWBC2-HP datasheet(28/96 Pages) STMICROELECTRONICS

28 / 96 page

Figure 33. Sequencer timing diagram overview

The disabling sequence is starting when list rolls over.

2.2.1.4

Programming

This section gives details about the HR-PWM SW configuration.

2.2.1.4.1

Sequencer configuration

The HR-PWM provides PWM0 & 1 primary outputs. PWM0 drives a half-bridge or one side of a full-bridge. PWM1

drives the other side of a full-bridge.

The HR-PWM provides also the complementary output of PWM0 and PWM1. By default, the complementary

signals are simply the inverse of the primary outputs. Hence, PWM0 and its complementary drive a half-bridge.

PWM1 and its complementary drive the other half-bridge. This default mode relies on the capability of the gate

driver to deal with anti-cross conduction.

If the gate drivers do not have anti-cross conduction function, the complementary outputs can be driven by PWM2

& PWM3. In this case, PWM0 & PWM2 drive one half-bridge. PWM1 & PWM3 drive the other half-bridge. To

enable this mode, set the bit PWM_2_3_AS_COMPLEMENT in the PWM_CONTROL_3 register.

The HR-PWM executes steps one by one. Each step codes a toggling of PWM outputs, a toggling of time capture

windows. Each step can be activated with a particular state of the FSK bit. Each step codes finally a delay before

applying the toggling of outputs or capture windows. At the moment the step delay elapses, the HR-PWM applies

the step toggling and moves to the next step.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 28/96

STWBC2-HP 数据表(PDF) 28 Page - STMicroelectronics