P9221-R3 Datasheet

© 2017 Integrated Device Technology, Inc.

3

October 20, 2017

13.1 Power Dissipation and Thermal Requirements................................................................................................................................37

13.2 Recommended Coils........................................................................................................................................................................38

13.3 Typical Application Schematic .........................................................................................................................................................39

13.4 Bill of Materials (BOM) .....................................................................................................................................................................40

14. Package Drawings......................................................................................................................................................................................42

15. Recommended Land Pattern......................................................................................................................................................................43

16. Special Notes: 52-WLCSP (AHG52) Package Assembly...........................................................................................................................44

17. Marking Diagram ........................................................................................................................................................................................44

18. Ordering Information...................................................................................................................................................................................44

19. Revision History..........................................................................................................................................................................................45

List of Figures

Figure 1. Pin Assignments – Bottom View..........................................................................................................................................................5

Figure 2. Efficiency vs. Output Load: VOUT = 12V .............................................................................................................................................12

Figure 3. Load Reg. vs. Output Load: VOUT = 12V............................................................................................................................................12

Figure 4. Efficiency vs. Output Load: VOUT = 9V ...............................................................................................................................................12

Figure 5. Load Reg. vs. Output Load: VOUT = 9V..............................................................................................................................................12

Figure 6. Efficiency vs. Output Load: VOUT = 5V ...............................................................................................................................................12

Figure 7. Load Reg. vs. Output Load: VOUT = 5V..............................................................................................................................................12

Figure 8. Rectifier Voltage vs. Load: VOUT = 12V ..............................................................................................................................................13

Figure 9. Rectifier Voltage vs. Load: VOUT = 9V ................................................................................................................................................13

Figure 10. Rectifier Voltage vs. Load: VOUT = 5V ................................................................................................................................................13

Figure 11. Current Limit vs. VILIM ........................................................................................................................................................................13

Figure 12. X and Y Misalignment........................................................................................................................................................................13

Figure 13. Max. Power vs. Misalignment: VOUT = 12V ........................................................................................................................................13

Figure 14. Enable Startup: VOUT = 12V; IOUT = 1.2A ............................................................................................................................................14

Figure 15. Transient Resp: VOUT = 12V; IOUT = 0 to 1.2A ....................................................................................................................................14

Figure 16. Transient Resp: VOUT = 12V; IOUT = 1.3A to 0 ....................................................................................................................................14

Figure 17. Functional Block Diagram..................................................................................................................................................................15

Figure 18. Example of Differential Bi-phase Decoding for FSK..........................................................................................................................21

Figure 19. Example of Asynchronous Serial Byte Format for FSK.....................................................................................................................22

Figure 20. Bit Encoding Scheme ........................................................................................................................................................................22

Figure 21. Byte Encoding Scheme .....................................................................................................................................................................22

Figure 22. Communication Packet Structure ......................................................................................................................................................22

Figure 23. Timing Diagram for a User Data Transfer from the P9221-R3 to the P9242-R3 ...............................................................................23

Figure 24. Typical P9221-R3 to P9242-R3 Data Transfer using the WP15WBD-RK Evaluation Kit ..................................................................24

Figure 25. State Diagram for User Data Transmission from the P9221-R3 to the P9242-R3.............................................................................25

Figure 26. State Diagram for Reading User Data Received from the P9242-R3................................................................................................27