P9221-R3 Datasheet

© 2017 Integrated Device Technology, Inc.

22

October 20, 2017

Each byte will comply with the start, data, parity, and stop asynchronous serial format structure shown in Figure 19:

Figure 19. Example of Asynchronous Serial Byte Format for FSK

Start

Stop

Parity

b0

1

2

3

4

5

6

7

b

b

b

b

b

b

b

9.3

Bit Encoding Scheme for ASK

As required by the WPC, the P9221-R3 uses a differential bi-phase encoding scheme to modulate data bits onto the power signal. A clock

frequency of 2kHz is used for this purpose. A logic ONE bit is encoded using two narrow transitions, whereas a logic ZERO bit is encoded using

one wider transition as shown below:

Figure 20. Bit Encoding Scheme

t CLK

ONE

ZERO

ONE

ZERO

ONE

ONE

ZERO

ZERO

9.4

Byte Encoding for ASK

Each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in Figure 21. Each byte has a start bit,

8 data bits, a parity bit, and a single stop bit.

Figure 21. Byte Encoding Scheme

Start

Stop

Parity

b0

1

2

3

4

5

6

7

b

b

b

b

b

b

b

9.5

Packet Structure

The P9221-R3 communicates with the base station via communication packets. Each communication packet has the following structure:

Figure 22. Communication Packet Structure

Preamble

Header

Message

Checksum