P9221-R3 Datasheet

© 2017 Integrated Device Technology, Inc.

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October 20, 2017

The P9221-R3 transfers data into the channel at a speed of 2Kbps. However, the channel is usually busy transmitting WPC standard

communication packets. There is a very small window in which the user data can transferred. Typically in the power transfer phase, the CEP

packet is sent every 150msec. In one second, there will be only 6 to 7 time slots in which the P9221-R3 can send a maximum of 10 bytes

(including the checksum and header) of user data in each slot. The maximum data transfer rate achieved between the P9221-R3 and the

P9242-R3 is 560bps.

The P9221-R3 will reset bit 0 in the Command register 004EHEX to 0 immediately after sending the data into the channel. The external MCU on

the receiver can periodically check bit 0 in the P9221-R3 register 004EHEX to get an acknowledgment of successful data transmission into the

channel.

Note: The P9221-R3 gives WPC standard communication packets priority over user data packets. User data packets have the lowest priority;

therefore during load transients, the P9221-R3 might skip sending user data packets and give priority to CEP and indicate the channel status

as busy in register 004EHEX.

The P9221-R3 does not wait for acknowledgement from the P9242-R3 or keep track of successful delivery of the data to the P9242-R3. The

P9221-R3 only functions as a messenger and relies upon the external MCUs on the receiver and transmitter boards to craft a lossless com-

munication protocol by adding intelligence into data they are transferring.

Figure 24. Typical P9221-R3 to P9242-R3 Data Transfer using the WP15WBD-RK Evaluation Kit

Note: The WP15WBD-RK is the evaluation kit available for the P9221-R3 and P9242-R3, which implements the typical application schematic

shown in Figure 28.