P9221-R3 Datasheet

© 2017 Integrated Device Technology, Inc.

16

October 20, 2017

8. Theory of Operation

The P9221-R3 is a highly-integrated, wireless power receiver targeted for 15W applications. The device integrates a full-wave synchronous

rectifier, low-dropout (LDO) linear regulator, and a 32-bit ARM® Cortex® -M0 processor to manage all the digital control required to comply with

the WPC-1.2 communication protocol.

Using the near-field inductive power transfer, the receiver converts the AC signal to a DC voltage using the integrated synchronous rectifier.

The capacitor connected to the output of the rectifier smooths the full-wave rectified voltage into a DC voltage. After the internal biasing circuit

is enabled, the “Synchronous Rectifier Control” block operates the switches of the rectifier in various modes to maintain reliable connections

and optimal efficiency.

The rectifier voltage and the output current are sampled periodically and digitized by the analog-to-digital converter (ADC). The digital

equivalents of the voltage and current are supplied to the internal control logic, which determines whether the loading conditions on the VRECT

pin indicate that a change in the operating point is required. If the load is heavy enough and brings the voltage at VRECT below its target, the

transmitter is set to a lower frequency that is closer to resonance and to a higher output power. If the voltage at VRECT is higher than its target,

the transmitter is instructed to increase its frequency. To maximize efficiency, the voltage at VRECT is programmed to decrease as the LDO’s

load current increases. The internal temperature is continuously monitored to ensure proper operation.

In the event that the VRECT voltage increases above 13.5V, the control loop disables the LDO and sends error packets to the transmitter in an

attempt to bring the rectifier voltage back to a safe operating voltage level while simultaneously clamping the incoming energy using the open-

drain SINK pin for VRECT linear clamping. The clamp is released when the VRECT voltage falls below the VOVP-DC minus VOVP-HYS. Refer to

Figure 17. The receiver utilizes IDT’s proprietary voltage clamping scheme, which limits the maximum voltage at the rectifier pin to 13.5V,

reducing the voltage stress on the output capacitors while eliminating the need for over-voltage protection (OVP) capacitors. As a result, it

provides a small application area, making it an industry-leading wireless power receiver for high power density applications. Combined with the

P9242-R3 transmitter, the P9221-R3 is a complete wireless power system solution.

8.1

LDO – Low Dropout Regulators

The P9221-R3 has three low-dropout linear regulators. The main regulator is used to provide the power required by the battery charger where

the output voltage can be set to either 9V or 12V. For more information about setting the output voltage, see section 8.2. It is important to

connect a minimum of a 20µF ceramic capacitance to the OUT pin.

The other two regulators, VDD5V and VDD18, are to bias the internal circuitry of the receiver. The LDOs must have local 1µF ceramic capacitors

placed as close as possible to the pins.

8.2

Setting the Output Voltage and Reference Q-factor Value – VOSET/Q-Fact

The output voltage on the P9221-R3 is programmed by connecting the center tap of the external resistors R34 and R33 to the VOSET/Q-Fact

pin as shown in the application schematic in Figure 28. The output voltage can be set to 9V or 12V. The recommended settings for R33 and

R34 are summarized in Table 6.

The default output voltage is set to 12V in the P9221-R3 Evaluation Board (R34 = 10kΩ; R33 = open). For applications where the transmitter

is capable of delivering only 5W, the P9221-R3 will automatically switch to 5V output to ensure 5W power delivery. The 5W option can be

disabled by changing the value of R33 as defined in Table 6. In this case, if the receiver is placed on a 5W transmitter, the receiver output pin

will be high impedance.

The VOSET/Q-Fact pin also sets the Q-factor value by adjusting R34 and R33 as shown in Table 6. The default value is set to 103 on the

P9221-R3 Evaluation Board. For development purposes, the Q-factor should be set to 20 to avoid prematurely triggering the Q-factor.