P9242-R3/RB Datasheet

© 2019 Integrated Device Technology, Inc.

3

May 17, 2019

12.1 Power Dissipation and Thermal Requirements .................................................................................................................................35

12.2 Recommended Coils .........................................................................................................................................................................36

12.3 Typical Application Schematic – P9242-R3-EVK included in WP15WBD-RK Kit..............................................................................36

12.4 Bill of Materials (BOM).......................................................................................................................................................................38

13. Package Outline Drawing...........................................................................................................................................................................41

14. Special Notes: NDG 48-VFQFPN Package Assembly...............................................................................................................................41

15. Marking Diagrams ......................................................................................................................................................................................41

16. Ordering Information...................................................................................................................................................................................42

17. Revision History..........................................................................................................................................................................................43

List of Figures

Figure 1. Pin Assignments..................................................................................................................................................................................5

Figure 2. Efficiency vs. Output Load: VOUT_RX = 12V.........................................................................................................................................11

Figure 3. Efficiency vs. Output Load: VOUT_RX = 9V...........................................................................................................................................11

Figure 4. Efficiency vs. Output Load: VOUT_RX = 5V...........................................................................................................................................11

Figure 5. Load Regulation vs. Output Load: VCC_5V in Schematic Figure 30 ................................................................................................11

Figure 6. Load Regulation vs. Output Load: LDO33.........................................................................................................................................11

Figure 7. Load Regulation vs. Output Load: LDO18.........................................................................................................................................11

Figure 8. Over-Current Limit vs. VILIM ...............................................................................................................................................................12

Figure 9. Voltage and Current Signal for Demodulation...................................................................................................................................12

Figure 10. Enable Startup...................................................................................................................................................................................12

Figure 11. Communication Packet during RX Load Step from 0 to 1.3A.............................................................................................................12

Figure 12. Communication Packet during RX Load Step from 1.3A to 0............................................................................................................12

Figure 13. Functional Block Diagram..................................................................................................................................................................13

Figure 14. Voltage Mode Envelope Detector......................................................................................................................................................16

Figure 15. Current Mode Envelope Detector......................................................................................................................................................16

Figure 16. NTC Thermistor Connection to TS Pin..............................................................................................................................................17

Figure 17. UVLO Threshold Definition................................................................................................................................................................19

Figure 18. Typical Application Diagram with Resonant Circuit...........................................................................................................................20

Figure 19. Example of Differential Bi-phase Encoding for FSK..........................................................................................................................21

Figure 20. Example of Asynchronous Serial Byte Format for FSK.....................................................................................................................22

Figure 21. Bit Decoding Scheme........................................................................................................................................................................22

Figure 22. Byte Decoding Scheme.....................................................................................................................................................................22

Figure 23. Communication Packet Structure......................................................................................................................................................22

Figure 24. Recommended Message Structure for the User Data Transfer from the P9242-R3 to the P9221-R3 for 8 Bytes of User Data.......24

Figure 25. Timing Diagram for the User Data Transfer from the P9242-R3 to the P9221-R3............................................................................24

Figure 26. Typical P9242-R3 to P9221-R3 Data Transfer using the WP15WBD-RK Evaluation Kit..................................................................25

Figure 27. State Diagram for User Data Transmission from the P9242-R3 to the P9221-R3 ............................................................................26