P9242-R3 datasheet(7/44 Pages) RENESAS

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P9242-R3/RB Datasheet

May 17, 2019

Pins

Name

Type

Function

OVP_CTL

Output

During the power transfer phase if an over-voltage has been detected on the VCOIL

pin, a logic HIGH output from this pin is used to scale down the voltage by driving the

external circuitry shown in Figure 30.

Q_DRV1

I/O

Control signal for the Q factor measurement circuit.

Q_DRV2

I/O

Control signal for the Q factor measurement circuit.

25, 26, 27, 28,

42, 43

RSV

Output

Reserved for internal use. Do not connect.

INT

��

Output

This pin transitions from HIGH to LOW when new data is available to be read.

The external MCU must reset the pin immediately after reading the user data. This

pin is in a push-pull configuration; add an external FET to make it an open-drain

connection.

GH_BRG2

Output

Gate driver output for the high-side FET of half bridge 2. Connect this pin to a series

12Ω resistor to the respective bridge FET gate.

BST_BRG2

Input

Bootstrap pin for half bridge 2. Connect an external capacitor from this pin to the

SW_BRG2 pin to generate a drive voltage higher than the input voltage.

SW_BRG2

Output

Switch node for half bridge 2.

GL_BRG2

Output

Gate driver output for the low-side FET of half bridge 2. Connect this pin to a series

12Ω resistor to the respective bridge FET gate.

GL_BRG1

Output

Gate driver output for the low-side FET of half bridge 1. Connect this pin to a series

12Ω resistor to the respective bridge FET gate.

SW_BRG1

Output

Switch node for half bridge 1.

BST_BRG1

Output

Bootstrap pin for half bridge 1. Connect an external capacitor from this pin to the

SW_BRG1 pin to generate a drive voltage higher than the input voltage.

GH_BRG1

Output

Gate driver output for the high-side FET of half bridge 1. Connect this pin to a series

12Ω resistor to the respective bridge FET gate.

DRV_VIN

Input

Input power supply for the internal gate drivers. Connect a 10µF capacitor from this

pin to ground.

VBRG_IN

Input

Bridge voltage input sense.

VDEM1

Input

High-pass filter input. Voltage demodulation pin for data packets based on coil

voltage variation; transmitted by the power receiver.

IDEMI

Input

High-pass filter input. Current demodulation pin for data packets based on coil current

variation; transmitted by the power receiver.

ISNS_OUT

Output

Input current sense output.

CSN

Input

Low-side input current sense (VBRIDGE).

CSP

Input

High-side input current sense (VIN).

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