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HMLQ25201T-R47MSR 数据表(PDF) 28 Page - Renesas Technology Corp |
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HMLQ25201T-R47MSR 数据表(HTML) 28 Page - Renesas Technology Corp |
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28 / 52 page  DA9080 High Current, Highly Configurable System PMIC with Four Bucks and One LDO Datasheet Revision 1.2 08-Feb-2022 CFR0011-120-00 28 of 51 © 2022 Renesas Electronics -2.5mV/usec -2.5mV/usec -1.25mV/usec -1.25mV/usec BUCK1 LDO BUCK2 BUCK3 BUCK4 Slot 3 Slot 2 Slot 1 Slot 0 EN pin Force Disable Bit Slot 0 2.5mV/usec 2.5mV/usec 3.3V 1.8V 3.3V 1.25mV/usec 1.25mV/usec Slot 1 Slot 2 Slot 3 1.1V 1.1V 3.0V(typ) tSS 1.32ms tSS 0.5ms(typ) tSS 0.72ms tSS 0.88ms Power down sequence by Disable bit Slot 0 : Buck1 Slot 1 : LDO Slot 2 : Buck2 and Buck3 Slot 3 : Buck4 PG1 Group : BUCK1, LDO PG2 Group : BUCK2, BUCK3, BUCK4 PG1 PG2 tPG_DLY 2ms tPG_DLY 2ms tPG_DLY 2ms tPG_DLY 10ms tPG_DLY 10ms BUCK1_NOT_OV && NOT_UV && SS_DONE LDO_NOT_OV && NOT_UV && SS_DONE BUCK2_NOT_OV && NOT_UV && SS_DONE BUCK3_NOT_OV && NOT_UV && SS_DONE BUCK4_NOT_OV && NOT_UV && SS_DONE tLDO_OFF 1.28ms tENH_DEBOUNCE 100ms tmask_UV 1.3ms Figure 9: Timing Diagram Example for Power-Down by DISABLE Bit |
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