DA9080

High Current, Highly Configurable System

PMIC with Four Bucks and One LDO

Datasheet

Revision 1.2

08-Feb-2022

CFR0011-120-00

3 of 51

© 2022 Renesas Electronics

12 I2C Communication ..................................................................................................................... 33

13 Register Definitions .................................................................................................................... 35

13.1 Register Map ....................................................................................................................... 35

13.2 Register Descriptions .......................................................................................................... 37

13.2.1

PMIC Function Registers..................................................................................... 37

13.2.2

Chip ID ................................................................................................................. 46

14 Package Information ................................................................................................................... 47

15 Ordering Information .................................................................................................................. 48

16 Application Information .............................................................................................................. 49

16.1 Recommended External Components ................................................................................ 50

16.2 Capacitor Derating .............................................................................................................. 50

Figures

Figure 1: System Diagram..................................................................................................................... 1

Figure 2: Block Diagram ........................................................................................................................ 6

Figure 3: UQFN Pinout Diagram (Top View)......................................................................................... 7

Figure 4: Measured Efficiency with Inductor 2520 .............................................................................. 17

Figure 5: Measured Efficiency with Low DCR Inductor 4141 .............................................................. 18

Figure 6: FSM States........................................................................................................................... 24

Figure 7: Timing Diagram Example for Power-Up .............................................................................. 26

Figure 8: Timing Diagram Example for Power-Down by EN Pin......................................................... 27

Figure 9: Timing Diagram Example for Power-Down by DISABLE Bit ............................................... 28

Figure 10: Timing Diagram Example for a Hiccup Cycle .................................................................... 30

Figure 11: I2C Start (S) and Stop (P)................................................................................................... 33

Figure 12: Single Write Command ...................................................................................................... 33

Figure 13: Consecutive Write Command ............................................................................................ 34

Figure 14: Single Read Command ...................................................................................................... 34

Figure 15: Consecutive Read Command ............................................................................................ 34

Figure 16: UQFN Package Outline Diagram ....................................................................................... 47

Figure 17: Application Diagram ........................................................................................................... 49

Tables

Table 1: Pin Description ........................................................................................................................ 7

Table 2: Pin Type Definition .................................................................................................................. 8

Table 3: Absolute Maximum Ratings..................................................................................................... 9

Table 4: Electrostatic Discharge Ratings .............................................................................................. 9

Table 5: Recommended Operating Conditions ..................................................................................... 9

Table 6: UQFN Ratings ....................................................................................................................... 10

Table 7: CH1 Buck Converter Electrical Characteristics ..................................................................... 10

Table 8: CH2 Buck Converter Electrical Characteristics ..................................................................... 12

Table 9: CH3 Buck Converter Electrical Characteristics ..................................................................... 14

Table 10: CH4 Buck Converter Electrical Characteristics ................................................................... 16

Table 11: LDO Electrical Characteristics............................................................................................. 19

Table 12: ADC Electrical Characteristics ............................................................................................ 20

Table 13: Supervision Electrical Characteristics ................................................................................. 20

Table 14: Quiescent Current Characteristics ...................................................................................... 21

Table 15: I2C Electrical Characteristics .............................................................................................. 22

Table 16: Digital I/O Electrical Characteristics .................................................................................... 23

Table 17: Register Map ....................................................................................................................... 35