HMLQ25201T-R47MSR datasheet(31/52 Pages) RENESAS

31 / 52 page

DA9080

High Current, Highly Configurable System

PMIC with Four Bucks and One LDO

Datasheet

Revision 1.2

08-Feb-2022

CFR0011-120-00

31 of 51

8.3

Power Good Indicator

Each supply has a power-good (PG) indicator that is set once the supply has been enabled and has

started correctly. After the supply becomes valid there is a delay, tPG, before the PG indicator is set.

For the bucks the PG indicator is the logical NOR of the UV and OV fault indicators.

During soft start the PG indicator is held low while the supply output is being ramped. When this

ramp is completed, and assuming no fault conditions exist, the PG indicator is set (after tPG). If a fault

exists once the soft-start voltage ramp is completed a fault will be registered and all supplies are

immediately disabled.

For the LDO there is a soft-start timeout period, tSS_TIMEOUT, during which UV fault detection is

blanked. After this period the LDO output is monitored for fault conditions.

During a dynamic voltage ramp the PG detection is blanked and held high. After the ramp has

completed the blanking is removed and the PG status is re-evaluated.

The PG indicators are cleared immediately in the event of a fault.

8.3.1

Monitoring Groups of Power Good Indicators via PG Pins

The output pins PG1 and PG2 are used to monitor the status of groups of PG indicators. Each pin's

group is determined by setting a register bit associated with an individual supply's PG indicator. A PG

pin is only set when all the PG indicators assigned to its group are set.

If no supplies are assigned to a PG pin then the pin is high impedance.

A delay is applied between the condition for the PG pin to be set and the PG1 or PG2 pin going high.

This delay is in addition to the delay added to the individual supply PG indicators.

The status of any PG indicator can be read back via I2C.

Buck Converters

DA9080 has four channels of switching buck converters, CH1 Buck to CH4 Buck. Each of the bucks

has an I2C programable voltage register, which defines the output voltage. The channels are phase

shifted by 0°, 90°, 180°, or 270°.

When a buck is enabled, its output voltage is controlled by a soft-start, output voltage ramp. When

the buck output reaches the target voltage, the power-good indicator status bit is set.

If a buck is enabled while the output capacitor is already charged (at a non-zero voltage) the buck will

not discharge the output during startup. The buck will not draw negative current while the soft-start

target voltage is lower than the actual output voltage and the voltage will then rise smoothly once the

soft-start voltage ramp exceeds the actual output voltage.

After a buck is disabled, the output voltage is completely discharged by the integrated pull-down

resistor before a new start-up is executed.

A pull-down resistor for each channel is enabled when the channel is disabled. This feature can be

disabled by setting dedicated register bits, each pull-down can be disabled individually per-buck.

9.1

Dynamic Voltage Control

CH1 and CH2 Buck converters do not support dynamic voltage control (DVC), their output voltage is

set by OTP register setting.

CH3 and CH4 Buck converters support DVC, with the following features:

■ When the value of the target voltage changes, the output voltage updates to the new target

value.

■ The DVC controller operates in pulse width modulation (PWM) mode (Note 1) with synchronous

rectification. During DVC operation the power-good indicator is available.

HMLQ25201T-R47MSR 数据表(PDF) 31 Page - Renesas Technology Corp

HMLQ25201T-R47MSR 数据表(HTML) 31 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表下载