SN250 datasheet(71/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

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dropped and the register bit SC_SPIRXOVF in the SC2_SPISTAT register is set. The RX

FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate

the error condition until the RX FIFO is drained. Once the DMA marks a RX error, there are

two conditions that will clear the error indication: setting the appropriate SC_TX/RXDMARST

bit in the SC2_DMACTRL register, or loading the appropriate DMA buffer after it has

unloaded.

Receiving a character always requires transmitting a character. In a case when a long

stream of receive characters is expected, a long sequence of (dummy) transmit characters

must be generated. To avoid software or transmit DMA initiating these transfers (and

consuming unnecessary bandwidth), the SPI serializer can be instructed to retransmit the

last transmitted character or to transmit a busy token (0xFF), which is determined by the

(or disabled) when the transmit FIFO is empty and the transmit serializer is idle, as indicated

by a cleared SC_SPITXIDLE register bit in the SC2_SPISTAT register.

Every time an automatic character transmission is started, a transmit underrun is detected

(as there is no data in transmit FIFO) and the register bit INT_SCTXUND in the

INT_SC2FLAG

transmission, the reception of new characters stops and the receive FIFO holds characters

just received.

Note:

The event Receive DMA complete event does not automatically mean receive FIFO empty.

Interrupts are generated by one of the following events:

●

Transmit FIFO empty and last character shifted out (0 to 1 transition of

SC_SPITXIDLE

)

●

Transmit FIFO changed from full to not full (0 to 1 transition of SC_SPITXFREE)

●

Receive FIFO changed from empty to not empty (0 to 1 transition of SC_SPIRXVAL)

●

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

●

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

●

Received and lost character while receive FIFO was full (Receive overrun error)

●

Transmitted character while transmit FIFO was empty (Transmit underrun error)

To generate interrupts to the CPU, the interrupt masks in the INT_SC2CFG and INT_CFG

SPI slave mode

The SC2 SPI Slave controller is enabled with the SC_SPIMST cleared in the SC2_SPICFG

The SC2 SPI Slave controller receives its clock from an external SPI master device and

supports rates up to 5Mbps.

The SC2 SPI Slave supports various frame formats depending upon the clock polarity

(SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see

Table 25). The register bits SC_SPIPOL, SC_SPIPHA, and SC_SPIORD are defined within

the SC2_SPICFG registers.

Note:

Switching the SPI configuration from SC_SPIPOL=1 to SC_SPIPOL=0 without subsequently

setting SC2_MODE=0 and reinitializing the SPI will cause an extra byte (0xFE) to be

transmitted immediately before the first intended byte.

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