SN250 datasheet(73/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

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FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate

the error condition until the RX FIFO is drained. Once the DMA marks a RX error, there are

two conditions that will clear the error indication: setting the appropriate SC_TX/RXDMARST

bit in the SC2_DMACTRL register, or loading the appropriate DMA buffer after it has

unloaded.

Receiving a character always causes a serialization of a transmit character pulled from the

transmit FIFO. When the transmit FIFO is empty, a transmit underrun is detected (no data in

transmit FIFO) and the register bit INT_SCTXUND in the INT_SC2FLAG register is set.

Because there is no character available for serialization, the SPI serializer retransmits the

last transmitted character or a busy token (0xFF), which is determined by the register bit

SC_SPIRPT

in the SC2_SPICFG register.

Note:

Even during a transmit underrun, the register bit SC_SPITXIDLE in the SC2_SPISTAT

the transmitter is not idle. After a complete byte has been clocked out, the bit

SC_SPITXIDLE

will be set and the register bit INT_SCTXIDLE in the INT_SC2FLAG

interrupt register will be set. The bits SC_SPITXIDLE and INT_SCTXIDLE will toggle in this

manner for every byte that is transmitted as an underrun.

When a transmit character is written to the (empty) transmit FIFO, the SC2_SPISTAT

written to the transmit FIFO until it is full, which causes the register bit SC_SPITXFREE in

the SC2_SPISTAT register to clear. When the SPI master begins to clock data out of the

MISO pin, the register bit SC_SPITXIDLE in the SC2_SPISTAT register clears (after the

first bit is clocked out) and indicates that not all characters are transmitted yet. After shifting

one transmit character to the MISO pin, space for one transmit character becomes available

in the transmit FIFO. This causes the register bit SC_SPITXFREE in the SC2_SPISTAT

causes the register bit SC_SPITXIDLE in the SC2_SPISTAT register to be set.

The SPI Slave controller must guarantee that there is time to move new transmit data from

the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI Slave

controller inserts a byte of padding onto the start of every new string of transmit data. After

slave select asserts and the bit SC_SPIRXVAL in the SC2SPISTAT register gets set at least

once, the following operation will hold true until slave select deasserts. Whenever the

transmit FIFO is empty and data is placed into the transmit FIFO, either manually or placed

through DMA, the SPI hardware will insert an extra byte onto the front of the transmission as

if this byte was placed there by software. The value of the byte that is inserted is chosen by

the bit SC_SPIRPT in the SC2_SPICFG. Take note that when this extra byte is transmitted,

the bit INT_SCTXUND will get set in the INT_SC2FLAG register.

Interrupts are generated by one of the following events:

●

Transmit FIFO empty and last character shifted out (0 to 1 transition of

SC_SPITXIDLE

)

●

Transmit FIFO changed from full to not full (0 to 1 transition of SC_SPITXFREE)

●

Receive FIFO changed from empty to not empty (0 to 1 transition of SC_SPIRXVAL)

●

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

●

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

●

Received and lost character while receive FIFO was full (Receive overrun error)

●

Transmitted character while transmit FIFO was empty (Transmit underrun error)

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