SN250 datasheet(22/130 Pages) STMICROELECTRONICS

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Functional description—system modules

SN250

22/130

The MAC resides in RX mode most of the time, and different format and address filters keep

non-intended

packets from using excessive RAM buffers, as well as preventing the CPU from being

interrupted. When the reception of a packet begins, the MAC reads 4-bit symbols from the

baseband and calculates the CRC. It assembles the received data for storage in a RAM

buffer. A RX MAC DMA provides direct access to the RAM memory. Once the packet has

been received, additional data is appended to the end of the packet in the RAM buffer

space. The appended data provides statistical information on the packet for the software

stack.

The primary features of the MAC are:

●

CRC generation, appending, and checking

●

Hardware timers and interrupts to achieve the MAC symbol timing

●

Automatic preamble, and SFD pre-pended to a TX packet

●

Address recognition and packet filtering on received packets

●

Automatic acknowledgement transmission

●

Automatic transmission of packets from memory

●

Automatic transmission after backoff time if channel is clear (CCA)

●

Automatic acknowledgement checking

●

Time stamping of received and transmitted messages

●

Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and

packet status)

●

IEEE 802.15.4 timing and slotted/unslotted timing

6.4

Packet Trace Interface (PTI)

The SN250 integrates a true PHY-level PTI for effective network-level debugging. This two-

signal interface monitors all the PHY TX and RX packets (in a non-intrusive manner)

between the MAC and baseband modules. It is an asynchronous 500 Kbps interface and

cannot be used to inject packets into the PHY/MAC interface. The two signals from the

SN250 are the frame signal (PTI_EN) and the data signal (PTI_DATA). The PTI is supported

by InSight Desktop.

6.5

XAP2b microprocessor

The SN250 integrates the XAP2b microprocessor developed by Cambridge Consultants

Ltd., making it a true system-on-a-chip solution. The XAP2b is a 16-bit Harvard architecture

processor with separate program and data address spaces. The word width is 16 bits for

both the program and data sides. Data-side addresses are always specified in bytes, though

they can be accessed as either bytes or words, while program-side addresses are always

specified and accessed as words. The data-side address bus is effectively 15 bits wide,

allowing for an address space of 32KB; the program-side address bus is 16 bits wide,

addressing 64k words.

The standard XAP2 microprocessor and accompanying software tools have been enhanced

to create the XAP2b microprocessor used in the SN250. The XAP2b adds data-side byte

addressing support to the XAP2 by utilizing the 15th bit of the data-side address bus to

indicate byte or word accesses. This allows for more productive usage of RAM, optimized

code, and a more familiar architecture for customers when compared to the standard XAP2.

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