SN250 datasheet(25/130 Pages) STMICROELECTRONICS

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SN250

Functional description—system modules

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the Simulated EEPROM implements an effective wear-leveling algorithm which effectively

extends the number of write cycles for individual tokens.

6.6.3

Flash Information Area (FIA)

The SN250 also includes a separate 1024-byte FIA that can be used for storage of data

during manufacturing, including serial numbers and calibration values. This area is mapped

to the data side of the address space, starting at address 0x5000. While this area can be

read as individual bytes, it can only be written to one word at a time, and may only be

erased as a whole. Programming of this special Flash page can only be enabled using the

SIF interface to prevent accidental corruption or erasure. The ZNet stack reserves a small

portion of this space for its own use, but the rest is available to the application.

6.6.4

RAM

The SN250 integrates 5KB of SRAM. Like the Flash memory, this RAM is also mapped to

both the program and data-side address spaces. On the program side, the RAM is mapped

to the top 2.5k words of the program address space. The program-side mapping of the RAM

is used for code when writing to or erasing the Flash memory. On the data side, the RAM is

also mapped to the top of the address space, occupying the last 5KB, as shown in Figure 3

and Figure 4.

Additionally, the SN250 supports a protection mechanism to prevent application code from

overwriting system data stored in the RAM. To enable this, the RAM is segmented into 32-

byte sections, each with a configurable bit that allows or denies write access when the

SN250 is running in Application Mode. Read access is always allowed to the entire RAM,

and full access is always allowed when the SN250 is running in System Mode. The ZNet

stack intelligently manages this protection mechanism to assist in tracking down many

common application errors.

6.6.5

Registers

Table 40 provides a short description of all application-accessible registers within the

SN250. Complete descriptions are provided at the end of each applicable Functional

Description section. The registers are mapped to the data-side address space starting at

address 0x4000. These registers allow for the control and configuration of the various

peripherals and modules. The registers may only be accessed as whole word quantities;

attempts to access them as bytes may result in undefined behavior. There are additional

registers used by the ZNet stack when the SN250 is running in System Mode, allowing for

control of the MAC, baseband, and other internal modules. These system registers are

protected from being modified when the SN250 is running in Application Mode.

6.7

Encryption accelerator

The SN250 contains a hardware AES encryption engine that is attached to the CPU using a

memory-mapped interface. NIST-based CCM, CCM*, CBC-MAC, and CTR modes are

implemented in hardware. These modes are described in the IEEE 802.15.4-2003

specification, with the exception of CCM*, which is described in the ZigBee Security

Services Specification 1.0. The ZNet stack implements a security API for applications that

require security at the application level.

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