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SN250

Functional description—system modules

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6.13

Sleep timer

The 16-bit sleep timer is contained in the always-powered digital block. It has the following

features:

●

Two output compare registers, with interrupts

●

Only Compare A Interrupt generates Wake signal

●

Further clock divider of 2N, for N = 0 to 10

The clock source for the sleep timer can be either the 32.768 kHz clock or the calibrated

1kHz clock (see Table 15). After choosing the clock source, the frequency is slowed down

with a 2N prescaler to generate the final timer clock (see Table 16). Legal values for N are 0

to 10. The slowest rate the sleep timer counter wraps is 216

∗ 210 / 1kHz ≈ 67109 sec. ≈

about 1118.48 min.

≈ 18.6 hrs.

The ZNet software allows the application to define the clock source and prescaler value.

Therefore, a programmable sleep/wake duty cycle can be configured according to the

application requirements.

6.14

Power management

The SN250 supports three different power modes: processor ACTIVE, processor IDLE, and

DEEP SLEEP.

The IDLE power mode stops code execution of the XAP2b until any interrupt occurs or an

external SIF wakeup command is seen. All peripherals of the SN250 including the radio

continue to operate normally.

The DEEP SLEEP power mode powers off most of the SN250 but leaves the critical chip

functions, such as the GPIO pads and RAM powered by the High Voltage Supply

(VDD_PADS). The SN250 can be woken by configuring the sleep timer to generate an

interrupt after a period of time, using an external interrupt, or with the SIF interface. Activity

on a serial interface may also be configured to wake the SN250, though actual reception of

data is not re-enabled until the SN250 has finished waking up. Depending on the speed of

the serial data, it is possible to finish waking up in the middle of a byte. Care must be taken

to reset the serial interface between bytes and discard any garbage data before the rest.

Another condition for wakeup is general activity on GPIO pins. The GPIO activity monitoring

is described in Section 7.1.

When in DEEP SLEEP, the internal regulator is disabled and VREG_OUT is turned off. All

GPIO output signals are maintained in a frozen state. Additionally, the state of all registers in

Table 15.

Sleep timer clock source selection

CLK_SEL

Clock Source

Calibrated 1kHz clock

32.768kHz clock

Table 16.

Sleep timer clock source prescaling

CLK_DIV[3:0]

Clock Source Prescale Factor

N = 0..10

N = 11..15

210

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