AD9511-VCOSLASHPCB datasheet(33/60 Pages) AD

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AD9511

Rev. A | Page 33 of 60

or power-down. When the SYNCB function is selected, the

FUNCTION pin does not act as either RESETB or PDB.

PDB: 58h<6:5> = 11b

The FUNCTION pin may also be programmed to work as an

asynchronous full power-down, PDB. Even in this full power-

down mode, there is still some residual VS current because

some on-chip references continue to operate. In PDB mode, the

FUNCTION pin is active low. The chip remains in a power-

down state until PDB is returned to logic high. The chip returns

to the settings programmed prior to the power-down.

See the Chip Power-Down or Sleep Mode—PDB section for

more details on what occurs during a PDB initiated power-

down.

DISTRIBUTION SECTION

As previously mentioned, the AD9511 is partitioned into two

operational sections: PLL and distribution. The PLL Section

was discussed previously. If desired, the distribution section can

be used separately from the PLL section.

CLK1 AND CLK2 CLOCK INPUTS

Either CLK1 or CLK2 may be selected as the input to the

distribution section. The CLK1 input can be connected to drive

the distribution section only. CLK1 is selected as the source for

the distribution section by setting Register 45h<0> = 1. This is

the power-up default state.

CLK1 and CLK2 work for inputs up to 1600 MHz. The jitter

performance is improved by a higher input slew rate. The input

level should be between approximately 150 mV p-p to no more

than 2 V p-p. Anything greater may result in turning on the

protection diodes on the input pins, which could degrade the

jitter performance.

See Figure 35 for the CLK1 and CLK2 equivalent input circuit.

These inputs are fully differential and self-biased. The signal

should be ac-coupled using capacitors. If a single-ended input

must be used, this can be accommodated by ac coupling to one

side of the differential input only. The other side of the input

should be bypassed to a quiet ac ground by a capacitor.

The unselected clock input (CLK1 or CLK2) should be powered

down to eliminate any possibility of unwanted crosstalk

between the selected clock input and the unselected clock input.

DIVIDERS

Each of the five clock outputs of the AD9511 has its own

divider. The divider can be bypassed to get an output at the

same frequency as the input (1×). When a divider is bypassed, it

is powered down to save power.

All integer divide ratios from 1 to 32 may be selected. A divide

ratio of 1 is selected by bypassing the divider.

Each divider can be configured for divide ratio, phase, and duty

cycle. The phase and duty cycle values that can be selected

depend on the divide ratio that is chosen.

Setting the Divide Ratio

The divide ratio is determined by the values written via the SCP

to the registers that control each individual output, OUT0 to

OUT4. These are the even numbered registers beginning at 4Ah

and going through 52h. Each of these registers is divided into

bits that control the number of clock cycles the divider output

stays high (high_cycles <3:0>) and the number of clock cycles

the divider output stays low (low_cycles <7:4>). Each value is 4

bits and has the range of 0 to 15.

The divide ratio is set by

Divide Ratio = (high_cycles + 1) + (low_cycles + 1)

Example 1:

Set the Divide Ratio = 2

high_cycles = 0

low_cycles = 0

Divide Ratio = (0 + 1) + (0 + 1) = 2

Example 2:

Set Divide Ratio = 8

high_cycles = 3

low_cycles = 3

Divide Ratio = (3 + 1) + (3 + 1) = 8

Note that a Divide Ratio of 8 may also be obtained by setting:

high_cycles = 2

low_cycles = 4

Divide Ratio = (2 + 1) + (4 + 1) = 8

Although the second set of settings produce the same divide

ratio, the resulting duty cycle is not the same.

Setting the Duty Cycle

The duty cycle and the divide ratio are related. Different divide

ratios have different duty cycle options. For example, if Divide

Ratio = 2, the only duty cycle possible is 50%. If the Divide

Ratio = 4, the duty cycle may be 25%, 50%, or 75%.

The duty cycle is set by

Duty Cycle = (high_cycles + 1)/[(high_cycles + 1) + (low_cycles + 1)]

See Table 17 for the values of the available duty cycles for each

divide ratio.

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