AD9511-VCOSLASHPCB datasheet(56/60 Pages) AD

56 / 60 page

AD9511

Rev. A | Page 56 of 60

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9511 offers both LVPECL and

LVDS outputs, which are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is a second

differential output option for the AD9511. LVDS uses a current

mode output stage with several user-selectable current levels.

The normal value (default) for this current is 3.5 mA, which

yields 350 mV output swing across a 100 Ω resistor. The LVDS

outputs meet or exceed all ANSI/TIA/EIA—644 specifications.

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled, logic (LVPECL)

outputs of the AD9511 provide the lowest jitter clock signals

available from the AD9511. The LVPECL outputs (because they

are open emitter) require a dc termination to bias the output

transistors. A simplified equivalent circuit in

A recommended termination circuit for the LVDS outputs is

shown in Figure 58.

3.3V

LVDS

100

DIFFERENTIAL (COUPLED)

3.3V

LVDS

100

Figure 41 shows

the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 56. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the desired switching threshold (1.3 V).

Figure 58. LVDS Output Termination

3.3V

LVPECL

SINGLE-ENDED

(NOT COUPLED)

3.3V

LVPECL

127

VT = VCC – 1.3V

See Application Note AN-586 on the ADI website at

www.analog.com for more information on LVDS.

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under less

than ideal operating conditions. In these application circuits,

the implementation and construction of the PCB is as

important as the circuit design. Proper RF techniques must be

used for device selection, placement, and routing, as well as for

power supply bypassing and grounding to ensure optimum

performance.

Figure 56. LVPECL Far-End Termination

3.3V

LVPECL

DIFFERENTIAL

(COUPLED)

3.3V

LVPECL

100

0.1nF

200

Figure 57. LVPECL with Parallel Transmission Line

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