AD9511-VCOSLASHPCB datasheet(5/60 Pages) AD

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AD9511

Rev. A | Page 5 of 60

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

In-Band Noise of the Charge Pump/

Phase Frequency Detector (In-Band

Means Within the LBW of the PLL)

The synthesizer phase noise floor is

estimated by measuring the in-band

phase noise at the output of the VCO and

subtracting 20logN (where N is the

N divider value).

@ 50 kHz PFD Frequency

−172

dBc/Hz

@ 2 MHz PFD Frequency

−156

dBc/Hz

@ 10 MHz PFD Frequency

−149

dBc/Hz

@ 50 MHz PFD Frequency

−142

dBc/Hz

PLL Figure of Merit

−218 +

10 × log (fPFD)

dBc/Hz

Approximation of the PFD/CP phase noise

floor (in the flat region) inside the PLL loop

bandwidth. When running closed loop this

phase noise is gained up by 20 × log(N)3.

PLL DIGITAL LOCK DETECT WINDOW4

Signal available at STATUS pin

when selected by 08h<5:2>.

Required to Lock

(Coincidence of Edges)

Selected by Register ODh.

Low Range (ABP 1.3 ns, 2.9 ns Only)

3.5

<5> = 1b.

High Range (ABP 1.3 ns, 2.9 ns)

7.5

<5> = 0b.

High Range (ABP 6 ns)

3.5

<5> = 0b.

To Unlock After Lock (Hysteresis)4

Selected by Register 0Dh.

Low Range (ABP 1.3 ns, 2.9 ns Only)

<5> = 1b.

High Range (ABP 1.3 ns, 2.9 ns)

<5> = 0b.

High Range (ABP 6 ns)

<5> = 0b.

1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.

2 CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section).

3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output.

4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

CLOCK INPUTS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUTS (CLK1, CLK2)1

Input Frequency

1.6

GHz

Input Sensitivity

1502

mV p-p

Jitter performance can be improved with higher slew

rates (greater swing).

Input Level

V p-p

Larger swings turn on the protection diodes and can

degrade jitter performance.

Input Common-Mode Voltage, VCM

1.5

1.6

1.7

Self-biased; enables ac coupling.

Input Common-Mode Range, VCMR

1.3

1.8

With 200 mV p-p signal applied; dc-coupled.

Input Sensitivity, Single-Ended

150

mV p-p

CLK2 ac-coupled; CLK2B ac bypassed to RF ground.

Input Resistance

4.0

4.8

5.6

kΩ

Self-biased.

Input Capacitance

1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.

2 With a 50 Ω termination, this is −12.5 dBm.

3 With a 50 Ω termination, this is +10 dBm.

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