AD9511-VCOSLASHPCB datasheet(51/60 Pages) AD

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AD9511

Rev. A | Page 51 of 60

Reg.

Addr.

(Hex)

Bit(s) Name

Description

Output Level

LVPECL

OUT0

(OUT1)

(OUT2)

Output Single-Ended Voltage Levels for LVPECL Outputs.

3D (3E) (3F) <3:2>

<3>

<2>

Output Voltage (mV)

490

330

805 (Default)

650

3D (3E) (3F) <7:4>

Not Used

40 (41)

<0>

Power-Down

LVDS/CMOS

OUT3

(OUT4)

Power-Down Bit for Both Output and LVDS Driver.

0 = LVDS/CMOS on (Default).

1 = LVDS/CMOS Power-Down.

Output Current

Level

LVDS

OUT3

(OUT4)

40 (41)

<2:1>

<2>

<1>

Current (mA)

Termination (Ω)

1.75

100

3.5 (Default)

100

5.25

40 (41)

<3>

LVDS/CMOS

Select

OUT3

(OUT4)

0 = LVDS (Default).

1 = CMOS.

40 (41)

<4>

Inverted CMOS

Driver

OUT3

(OUT4)

Affects Output Only when in CMOS Mode.

0 = Disable Inverted CMOS Driver (Default).

1 = Enable Inverted CMOS Driver.

40 (41)

<7:5>

Not Used.

42 (43) (44) <7:0>

Not Used.

<0>

Clock Select

0: CLK2 Drives Distribution Section.

1: CLK1 Drives Distribution Section (Default).

<1>

CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b).

<2>

CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b).

<3>

Prescaler Clock

Power-Down

1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b).

<4>

REFIN Power-

Down

1 = Power-Down REFIN (Default = 0b).

<5>

All Clock Inputs

Power-Down

1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;

(Default = 0b).

<7:6>

Not Used.

46 (47)

(48) (49)

<7:0>

Not Used.

AD9511-VCO/PCB 数据表(PDF) 51 Page - Analog Devices

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AD9511-VCO/PCB 数据表(PDF) 51 Page - Analog Devices

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